Patents by Inventor Armin Klumpp
Armin Klumpp has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230207621Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.Type: ApplicationFiled: February 17, 2023Publication date: June 29, 2023Inventors: Peter RAMM, Armin KLUMPP
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Patent number: 11610967Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.Type: GrantFiled: July 22, 2020Date of Patent: March 21, 2023Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Peter Ramm, Armin Klumpp
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Publication number: 20230043673Abstract: A cryo-compatible quantum computing arrangement includes a microelectronic quantum computing component having a substrate structure, a plurality of first contact elements and a plurality of conductive feedthroughs through the substrate structure, wherein the conductive feedthroughs are electrically connected on a first main surface area of the substrate structure to associated first contact elements of the microelectronic quantum computing component, and a further microelectronic component having a plurality of second contact elements, wherein on a second main surface area of the substrate structure, the conductive feedthroughs are electrically connected to associated second contact elements of the further microelectronic component, and wherein the conductive feedthroughs each include, between the first and second contact elements, a layer element including a first material that is superconducting at a quantum computing operating temperature, and a filling element including a second material that is electricaType: ApplicationFiled: July 25, 2022Publication date: February 9, 2023Inventors: Peter RAMM, Josef WEBER, Armin KLUMPP
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Publication number: 20210036105Abstract: The invention relates to a vertical compound semiconductor structure having a substrate with a first main surface and an opposite second main surface, a vertical channel opening extending completely through the substrate between the first main surface and the second main surface and a layer stack arranged within the vertical channel opening. The layer stack includes an electrically conductive layer arranged within the vertical channel opening and a compound semiconductor layer arranged within the vertical channel opening. The compound semiconductor layer includes a compound semiconductor layer arranged on the electrically conductive layer and connected galvanically to the electrically conductive layer. Further, the invention relates to a method for producing such a vertical compound semiconductor structure.Type: ApplicationFiled: July 22, 2020Publication date: February 4, 2021Inventors: Peter RAMM, Armin KLUMPP
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Publication number: 20210035915Abstract: The invention relates to a semiconductor structure including a substrate with a first main surface located on a first substrate side and a second main surface located on an opposite second substrate side as well as a vertical via extending completely through the substrate between the first main surface and the second main surface. On the first substrate side, a metallization layer that is connected galvanically to the via is arranged in the region of the via. A compound semiconductor layer connected galvanically to the metallization layer is arranged on the metallization layer. Further, the invention relates to a method for producing such a semiconductor device structure.Type: ApplicationFiled: July 29, 2020Publication date: February 4, 2021Inventor: Armin KLUMPP
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Patent number: 8324022Abstract: A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a first contact pad at a first main side of the first substrate; providing a second substrate with a second main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the second main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the second main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact areaType: GrantFiled: September 17, 2008Date of Patent: December 4, 2012Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Peter Ramm, Armin Klumpp
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Publication number: 20100289146Abstract: A method for manufacturing a three-dimensional, electronic system includes: providing a first integrated circuit structure in a first substrate, wherein the first integrated circuit structure has a contact pad at a first main side of the first substrate; providing a second substrate with a main side; forming a vertical contact area in the second substrate; after step (c) forming a semiconductor layer on the main side of the second substrate; forming a semiconductor device of a second integrated circuit structure in the second substrate with the semiconductor layer; removing the substrate material from a side of the second substrate opposite the main side, so that the vertical contact area at the opposite side is electrically exposed; arranging the first and second substrates on top of each other aligning the vertical contact area with the contact pad, so that an electrical connection between the first and second integrated circuit structures is produced via the vertical contact area and the contact pad.Type: ApplicationFiled: September 17, 2008Publication date: November 18, 2010Inventors: Peter Ramm, Armin Klumpp
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Patent number: 7027283Abstract: The present invention provides a mobile holder for a wafer, which comprises a base element, a first fixing means and a second fixing means. The first fixing means is configured to allow a wafer to be fixed to the base element. The second fixing means is configured to fix the mobile holder to a support for said mobile holder.Type: GrantFiled: July 30, 2001Date of Patent: April 11, 2006Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.Inventors: Christof Landesberger, Armin Klumpp, Martin Bleier
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Patent number: 6756288Abstract: In a method of dicing a wafer, which comprises a plurality of individual circuit structures, a trench is first defined between at least two circuit structures on one face of the wafer. Subsequently, the trench is deepened down to a defined depth. Following this, one face of the wafer has fixed thereto a re-detachable intermediate support composed of a fixed intermediate support substrate and an adhesive medium which is applied to said intermediate support substrate and which can specifically be modified in terms of its adhesive strength, whereupon the wafer is dry-etched from the opposite face so that circuit chips are obtained which are connected to one another only via the intermediate support. Subsequently, the circuit chips are removed from the intermediate support.Type: GrantFiled: June 3, 2002Date of Patent: June 29, 2004Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E.V.Inventors: Michael Feil, Christof Landesberger, Armin Klumpp, Erwin Hacker
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Publication number: 20040037692Abstract: The present invention provides a mobile holder for a wafer, which comprises a base element, a first fixing means and a second fixing means. The first fixing means is configured to allow a wafer to be fixed to the base element. The second fixing means is configured to fix the mobile holder to a support for said mobile holder.Type: ApplicationFiled: June 10, 2003Publication date: February 26, 2004Inventors: Christof Landesberger, Armin Klumpp, Martin Bleier
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Patent number: 6548391Abstract: The present invention relates to a method of connecting two semiconductor components comprising the steps of providing in a first main surface of a first semiconductor substrate first component structures including first contact areas, forming in said first semiconductor substrate via holes filled with electrically conductive material and electrically insulated from said first semiconductor substrate, said via holes extending down to the second main surface of the first semiconductor substrate and being connected in an electrically conductive manner to said first contact areas via an electrically conductive connection material on the first main surface of said first semiconductor substrate, forming on the second main surface of the first semiconductor substrate first lands which are connected in an electrically conductive manner to the first contact areas via the electrically conductive material in the via holes, providing on a second semiconductor substrate second component structures including second contacType: GrantFiled: March 18, 2002Date of Patent: April 15, 2003Assignee: Fraunhofer-Gesellschaft zur Foerderung der Angewandten Forschung E. V.Inventors: Peter Ramm, Armin Klumpp
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Patent number: 6328841Abstract: In a method of connecting a first and a second silicon wafer, the first silicon wafer is first provided with a polyimide layer on a main surface thereof. Subsequently, a plasma-induced reaction between the polyimide layer and water is performed. A plasma-induced reaction is also performed between a main surface of the second silicon wafer and chlorine. The main surface of the second silicon wafer is then subjected to a treatment with hydrolyzed triethoxysilylpropanamine. Following this, the surfaces of the two silicon wafers, which have been subjected to the plasma-induced reactions, are joined together so as connect the silicon wafers permanently.Type: GrantFiled: November 5, 1999Date of Patent: December 11, 2001Assignee: Fraunhofer-Gesellschaft zur Foerderungdder Angewandten Forschung, e.V.Inventors: Armin Klumpp, Christof Landesberger
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Patent number: 5506008Abstract: Lacquer films sensitive to ultraviolet (UV) and/or electron beam radiation re applied to substrates as masking layers by a process known as the "spin on process". This invention is a new method of applying a lacquer film sensitive to UV and/or electron beam radiation. A vinyl-containing substance and a linear or cyclic siloxane are vaporized and then deposited onto the substrate to be masked. In the preferred embodiment of the invention, the substances utilized are octamethylcyclotetrasiloxane and trivinylmethylsilane.Type: GrantFiled: July 19, 1994Date of Patent: April 9, 1996Assignee: Fraunhofer-Gesellschaft zur Forderung Der Angewandten Forschung e.V.Inventors: Armin Klumpp, Erwin Hacker
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Patent number: 5262358Abstract: A silicate layer, which is especially used as an intermediate oxide insulation layer in an integrated circuit for levelling topographic irregularities, is produced by the following method steps: photo-induced polymerization of polysiloxane by means of vapor-phase reaction taking as a basis an SiO-containing or an SiC-containing organic compound together with an O.sub.2 -containing and/or an N.sub.Type: GrantFiled: June 22, 1992Date of Patent: November 16, 1993Assignee: Fraunhofer-Gesellschaft zur Forderung der angewandten Forschung e.V.Inventors: Hermann Sigmund, Armin Klumpp