Abstract: A method for advantageously translating high-level language codes for data processing using a reconfigurable architecture, memories addressable internally from within said reconfigurable architecture, and memories external to said reconfigurable architecture, may include constructing a finite automaton for computation in such a way that a complex combinatory network of individual functions is formed, assigning memories to the network for storage of operands and results, and separating external memory accesses for providing a transfer of at least one of operands and results as data from an external memory to a memory addressable internally by the reconfigurable architecture.

Abstract: Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

Abstract: A method is described for debugging reconfigurable hardware. In one example embodiment, debugging information is written for each configuration cycle into a memory which is then evaluated by a debugger.

Abstract: Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

Abstract: Programming of modules which can be reprogrammed during operation is described. Partitioning of code sequences is also described.

Abstract: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Abstract: A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: Procedures and methods for managing and transmitting data within multidimensional systems of transmitters and receivers are described. Splitting a data stream into a plurality of independent branches and subsequent merging of the individual branches to form a data stream is to be performable in a simple manner, the individual data streams being recombined in the correct sequence. This method may be particularly useful for executing reentrant code. The method is well suited, in particular, for configurable architectures; particular attention is paid to the efficient control of configuration and reconfiguration.

Abstract: A method for efficiently debugging a program defining a plurality of configurations to be successively processed on a dynamically reconfigurable architecture including a plurality of logic elements cooperating with each other. The method includes storing data in a memory in a configuration-conforming manner, the data generated by executing a configuration forming part of the program on the reconfigurable architecture, and including algorithmically relevant state data of the program that is associated with at least one of the configurations. The method further includes subsequently continuing execution of the program, the execution including a reconfiguration, and detecting an error based on stored state data, wherein for each state for which corresponding state data is to be stored, the state remains unchanged at least until the corresponding state data is stored.

Abstract: A method for translating high-level languages to reconfigurable architectures is disclosed. The method includes building a finite automaton for calculation. The method further includes forming a combinational network of a plurality of individual functions in accordance with the structure of the finite automaton. The method further includes allocating a plurality of memories to the network for storing a plurality of operands and a plurality of results.

Abstract: An example method of controlling a data processing system having a cellular structure. The method includes transmitting a first configuration word to a first processing unit in the cellular structure. The method also includes processing data with the first processing unit in accordance with the first configuration word. The method also includes transmitting a second configuration word to the first processing unit. The method also includes transmitting a reconfiguration signal to the first unit, the reconfiguration signal indicating that the first unit should begin processing data in accordance with the second configuration word. If the first processing unit has completed processing data in accordance with the first configuration word prior to when the reconfiguration signal is received by the first processing unit, data may be processed by the first processing unit in accordance with the second configuration word.