Abstract: An array of ALUs and a controlling and controlling unit providing the array sequentially ordered subapplications, wherein an ALU signals completion of execution of a subapplication to the controlling unit, which then provides a next sequential subapplication to the requesting ALU.

Abstract: At the inputs and/or outputs, memories are assigned to a reconfigurable module to achieve decoupling of internal data and in particular decoupling of the reconfiguration cycles from the external data streams (to/from peripherals, memories, etc.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the processed results to the external memory.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. Each processor has a processing element, an input register and an output register, each of which is connected to a segment of the segmented bus system. The segmented bus system provides a plurality of selectable data paths between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: An array of ALUs and a controlling and controlling unit providing the array sequentially ordered subapplications, wherein an ALU signals completion of execution of a subapplication to the controlling unit, which then provides a next sequential subapplication to the requesting ALU.

Abstract: An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A method for coordinating the transfer of data between external memory and an array of data processors using address generators and local memory. The method includes loading a plurality of groups of operands into local memory, processing the plurality of groups of operands on a single processor, and then returning the process results external memory.

Abstract: An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.

Abstract: An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array processor and each memory whereby a plurality of selectable data paths are provided between each processor and other processors, between each processor and each memory and between each memory and other memories.

Abstract: A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Abstract: A multi-processor cache and bus interconnection system. A multi-processor is provided a segmented cache and an interconnection system for connecting the processors to the cache segments. An interface unit communicates to external devices using module IDs and timestamps. A buffer protocol includes a retransmission buffer and method.

Abstract: A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel.

Abstract: A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.

Abstract: An array data processor employs a plurality of address generators for communicating between groups of the data processors and external devices. In another aspect, the data processor employs a buffer system having a plurality of pointers that allow for retransmission of data from the buffer upon transfer failure.

Abstract: A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separate communication start and end points.

Abstract: An array processor composed of processor cells that are programmed by a controlling unit, and that are reprogrammed when a cell has finished a current data processing operation, even while other cell continue to process data with their current programming.

Abstract: A parallel processing array processor has a plurality of arithmetic units and a unit that manages barrier instructions whereby processing of program sequences may be coordinated. The array processor further comprises a hierarchy of assigned units whereby multiple program sequences may be processed in parallel.

Abstract: A method wherein a plurality of data processors are associated with application IDs whereby the array processes a plurality of applications in parallel.