Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: A device is provided that mitigates the effects of an optical network unit (ONU) that is in a rogue state. A main processor is arranged as part of a monolithic semiconductor chip, the main processor configured to process signals from an optical telecommunication connection. A laser driver controls a laser coupled to the laser driver. Hardware logic is arranged as part of the monolithic semiconductor chip and arranged physically separate from the main processor. The hardware logic independently effects the laser driver to turn the laser off or reduce power output of the laser significantly to mitigate the effects of the ONU in the rogue state.

Abstract: A device is provided that mitigates the effects of an optical network unit (ONU) that is in a rogue state. A main processor is arranged as part of a monolithic semiconductor chip, the main processor configured to process signals from an optical telecommunication connection. A laser driver controls a laser coupled to the laser driver. Hardware logic is arranged as part of the monolithic semiconductor chip and arranged physically separate from the main processor. The hardware logic independently effects the laser driver to turn the laser off or reduce power output of the laser significantly to mitigate the effects of the ONU in the rogue state.

Abstract: The described implementations relate a Passive Optical Network (PON). In one implementation, the PON includes an Optical Network Unit (ONU) that has at least one transmitter subsystem component and an associated optical transmitter. The at least one transmitter subsystem component may be configured to be in an enabled state during a timeslot period assigned to the ONU for transmitting an upstream data burst and a disabled state after the timeslot ends.

Abstract: Embodiments related to light emitter control are described and depicted.

Abstract: Embodiments related to light emitter control are described and depicted.

Abstract: An arrangement includes a data interface that has a data input for receiving first data packets from a synchronous network that can be connected to the data input. The arrangement also has a network terminal and a packet-oriented synchronous data connection that extends between the data interface and the network terminal. The data interface is designed to derive the clock of the data connection from the clock of the synchronous network.

Abstract: A digitally controlled circuit for reducing the phase modulation of a signal. The circuit has a multiphase clock generator that produces n phases of a clock that is m-times the signal. The circuit further has a multiplexer with n inputs for the n phases of the clock and with one output which supplies the output signal. The output signal and the signal are connected to the inputs of a phase comparator. The output signal of the comparator is supplied to a sigma-delta modulator whose output signals are used for controlling the multiplexer. A jittered input signal is compared in the phase comparator with a master clock. The determined phase difference is integrated in a sigma-delta modulator. The aim of the circuit is to generate a clock without jitter, digitally and without using external components. This circuit provides 20 dB/decade attenuation of the jitter received in the SYNC signal, based on the P-regulator characteristic.