Abstract: A method and apparatus of wiring a twisted signal such as those that may be used in a twisted bitline architecture of a memory. The twisted bitline architecture includes mixing twisted bitline pairs and hybrid twisted bitline pairs to form a memory array. The twisted bitline pair includes two bitlines, such as a bitline-true line and a bitline-complementary line. The bitlines are formed on two metal layers, M0 and M1. Metal layer M1 is used to accomplish a twist in the bitline and allowing the bitline on metal layer M0 to be moved to metal layer M1, and the bitline on metal layer M1 to be moved to metal layer M0. The hybrid twisted bitline pair includes two bitlines. The first bitline extending over approximately one-half of the width of the memory array on metal layer M0. The second bitline extends over one-half of the width of the memory array on metal layer M1 and the remained on metal layer M1.

Abstract: An automatic method for the generation of a logical hardware test pattern in memory circuits is based on a given physical pattern. The method includes backwards transformation from a given set of logical data patterns. Since the method is automatic, no knowledge of data scrambling inside the memory circuit is required.

Abstract: A memory bank, in accordance with the present invention includes a plurality of memory sub-units, each memory sub-unit being divided by sense amplifier banks wherein adjacent memory sub-units share the sense amplifier bank therebetween. Redundancy regions are also included which are disposed in the memory sub-units and sharing circuitry therewith. The redundancy regions are located at a first end portion and a second end portion of the memory bank, the first and second end portions being disposed at opposing ends of the memory bank. A central sense amplifier bank is disposed between a first half and a second half of the memory bank wherein failed devices in the first half of the memory bank are replaced by a device in the redundancy region at the first end portion and failed devices in the second half of the memory bank are replaced by a device in the redundancy region at the second end portion such that sense amplifier contention is prevented for the central sense amplifier bank.