Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: A photo-transistor in MOS thin-film technology operable with alternating voltages is comprised of a semiconductor body (3) composed of polycrystalline silicon having source (4) and drain (5) zones therein spaced apart by an undoped channel region (13) and having a gate electrode (1, 10) separated from the semiconductor body (3) by a SiO.sub.2 layer (2) produced by thermal oxidation. These phototransistors are easily and reproducably produced and are characterized by low threshold voltages and a good transistor characteristic curve. Thus, these photo-transistors are well suited for use as sensor elements, opto-couplers, time-delay elements and as photo-transistors in VLSI circuits.

Abstract: A process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate wherein n-doped zones are produced in the p-doped substrate and insulated npn-bipolar transistors are formed into the n-doped zones. The n-zones form the collectors of the transistors and are modified according to conventional technology by additional process steps such that bipolar transistors are formed which are self-aligning both between the emitter and the base and also between the base and collector with extremely low-ohmic base terminals consisting of polysilicon and a silicide. Storage capacitances can also additionally be integrated into the structure. The use of the base terminals thus produced permits very small lateral emitter-collector distances. The combination of dynamic CMOS memory cells with fast bipolar transistors is made possible by the integration of the storage capacitances.

Abstract: A method for the manufacture of bipolar transistor structures with self-adjusted emitter and base regions wherein the emitter and base regions are generated by an out-diffusion from doped polysilicon layers. Dry etching processes which produce vertical etching profiles are employed for structuring the SiO.sub.2 and polysilicon layers. The employment of additional oxidation processes for broadening the lateral edge insulation (see arrow 9) during the manufacture of the bipolar transistor structures enables self-adjusted emitter-base structures with high reproducibility in addition to advantages with respect to the electrical parameters. The method is employed for the manufacture of VLSI circuits in bipolar technology.

Abstract: A monolithic static memory cell has a region of a first conductivity type extending from the upper surface of a semiconductor layer of a second conductivity type carried on a semiconductor body of the first conductivity type and connected to a first drive line. A first zone of the semiconductor layer adjacent the region is covered by a gate connected to a second drive line and separated from the semiconductor layer by a gate insulator. A second zone adjacent the first zone is covered by a conductive coating connected to a supply terminal, the conductive coating being separated from the surface of the semiconductor layer by a thin electrically insulating layer which admits a tunnel current between the surface of the semiconductor layer and the conductive coating.

Abstract: Production of high bit density memory cells using six selective, vertically aligned, reactive plasma etching steps. A gate oxide layer is applied to the boundary surface of the semiconductor layer and has a polysilicon layer which is highly doped and covered with a first intermediate oxide layer. A drive line and the gate are first formed. Sections of the drive line at the ends thereof are removed by isotropic etching and the resulting recesses are filled in a thermal oxidation step. The portion of the gate oxide layer adjacent the structured parts is removed by a second etching step. A second polysilicon layer is deposited, highly doped and covered with a second intermediate oxide layer. Another drive line having a part contacting a doped region in the semiconductor layer, the region being formed by ion implantation, is structured by a third etching step.