Abstract: A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.

Abstract: A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.

Abstract: The present invention relates to a method for generating a scan chain in a custom electronic circuit design with a plurality of storage elements. Said method comprises the steps of providing a schematic, propagating all scan inputs and all scan outputs of the storage elements to a top level of the design hierarchy, and declaring each scan input and each scan output on the top level as primary input and primary output, respectively. Said method comprises further the steps of adjusting a layout of the custom circuit according to the schematic, building up the scan chain according to a predetermined algorithm, and annotating the scan chain back into the schematic.

Abstract: The present invention relates to a scan chain and related cell design structures in a custom electronic circuit design with a plurality of storage elements. All scan inputs and all scan outputs of the storage elements are propagated to a top level of the design hierarchy in design. Each scan input and each scan output on the top level is declared a primary input and primary output, respectively. Propagating all the inputs and outputs of the storage elements to this level improves the wireability of the scan chain.