Abstract: A method of monitoring performance for transactions performed by a mobile computing device with a transaction system is described. A set of performance metrics related to a transaction is defined. For a transaction, at least some of the set of performance metrics from that transaction are captured at the mobile computing device and provided so that a report on the set of performance metrics can be provided for the transaction. This report may be provided by a monitoring service external to the mobile computing device.

Abstract: The invention pertains mainly to a processor for the calculation of the discrete Fourier transform, comprising a real-time testing device. The device according to the invention uses the theorem of Parseval to ascertain that the processor is working properly. The device according to the invention uses, for example, an adder and a multiplier to calculate either the discrete Fourier transform or the members of the equation. Thus, by using temporal redundancy, the complexity, area and price of the processor are reduced. The invention is applied mainly to the calculation of spectra.

Abstract: A device and a method are used to test integrated circuits, especially P.L.A.s. The possible faults of a circuit to be tested are determined including logic faults caused by the physical structure and relative position of the circuit elements in the integrated logic circuit. On the basis of the faults, a set of test vectors is determined, each fault modifying at least one of the test vectors applied to the circuit to be tested. It is possible to use test vectors which are modified by the greatest number of possible faults. By determining the test vectors on the basis of the faults which are to be detected, the tests can use a small number of vectors while, at the same time, there is certainty that it will be possible to detect all the faults in a given circuit. Advantageously, a hierarchically-organized set of cells is determined with certain cells consisting of small cells. The method and device can be used to test P.L.A.

Abstract: A device for the testing of electrical circuits and a circuit comprising the said device are disclosed. The testing device is used to test electrical circuits by the generation of test vectors and the compression of the signal at the output of the device to be tested. The device of the present invention uses the same shift register, certain cells of which are looped at the input, by means of an exclusive-OR logic gate, to generate test vectors and perform signature analysis. Thus it is possible to test electrical circuits themselves as well as the input/output buses. The invention can be applied, in particular, to the testing of computers, microprocessors, memories, fast Fourier transform calculators, adders, multipliers, combinational logic systems or circuits including combinational logic systems or circuits that have internal memorizing devices.

Abstract: The invention pertains mainly to a reconfigurable computing device. The main object of the invention is a computer comprising redundant elements. The computer according to the present invention can function when there is a failure of one of the elements that constitute it. In this case, the redundant element takes the place of the malfunctioning element. Should the computer according to the present invention be in a critical stage, i.e. a situation where any interruption in computation would have serious consequences, the reconfiguring of the system is postponed to a later instant corresponding to the end of the critical stage. The invention applies mainly to the performing of digital computations.

Abstract: An in line testing device for a circuit calculating discrete Fourier transform as well as a circuit including such a device. The device has a processor for calculating the discrete Fourier transform and a processor effecting in line checking of the calculation of the discrete Fourier transform.