Abstract: In a method of optimizing power consumption in an integrated circuit, a physically implemented circuit design meeting at least one timing constraint is provided. A design block of the physically implemented circuit design having a high toggle rate pattern is identified. A power optimized transformation type of numerous power optimized transformation types is selected. The power optimized transformation type is applied to the design block of the physically implemented circuit design. A modified physically implemented circuit design is generated, where the modified physically implemented circuit design is power optimized.

Abstract: Method, apparatus, and computer readable medium for directed physical implementation of a circuit design for an integrated circuit is described. One aspect of the invention relates to implementing a circuit design for an integrated circuit. Matching elements between an original version of the circuit design and a modified version of the circuit design are identified. The original version includes an original implementation. The modified version is partially placed and routed to establish a guided implementation having guided placements and guided routes for the matching elements based on placements and routes from the original implementation. Actual timing characteristics for the guided placements and the guided routes are obtained. Since the routes in the guided implementation are fully implemented, actual timing characteristics can be exactly determined. Placement and routing in the modified implementation are completed using the actual timing characteristics.

Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, matching elements between a modified version of the circuit design and an implemented version of the circuit design are identified. Recommended placements for the matching elements are established based on placement information from the implemented version of the circuit design. An initial placement of the modified version of the circuit design is generated using the recommended placements. Timing-critical elements in the initial placement are identified. Locked placements for elements other than the timing-critical elements are established. An optimized placement of the modified version of the circuit design is generated using the locked placements.