Patents by Inventor Arnaud GAZDA
Arnaud GAZDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230297867Abstract: Method for implementing a graph (G) comprising a plurality of vertices (V) and links (E) between the vertices, a set (R) being a collection of subsets (Ri) of said a given number of vertices (Rik) comprising: in said set (R), selecting subsets (Ri, Rj), called pre-selected subsets, such that a tree (Ti, Tj) is associated respectively to said tree (Ti, Tj), said associated trees (Ti, Tj) being pairwise disjoint; comparing the number of vertices (Rik) associated to each of the pre-selected subset, among the pre-selected subsets, choosing the subset for which the number of vertices is the highestType: ApplicationFiled: March 10, 2023Publication date: September 21, 2023Applicant: BULL SASInventors: Arnaud GAZDA, Simon MARTIEL, Jon OILLARBURU
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Publication number: 20230297351Abstract: Method for implementing a quantum circuit comprising a plurality of qubits as well as operators executed on said qubits, said operators comprising a sequence of ? 4 Pauli rotation gates, a surface code layout comprising an arrangement of said quantum circuit on a quantum chip, the arrangement comprising at least a tree with a plurality of subtrees, at each rotation gate corresponding a subtree of the tree, the method comprising: generating iteratively a directed acyclic graph of said quantum circuit, a front layer of the DAG being a set of rotations that can be effectively implemented at each iteration, and selecting in said front layer of the DAG a subset, called selected subset, of said set of rotations among subsets, called non intersecting subsets, in which the subtrees are arranged not to intersect.Type: ApplicationFiled: March 15, 2023Publication date: September 21, 2023Applicant: BULL SASInventors: Arnaud GAZDA, Simon MARTIEL, Jon OILLARBURU
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Publication number: 20230297868Abstract: Method for implementing a graph (G) comprising a plurality of vertices (V) and links (E) between the vertices, a set (R) being a collection of subsets (Ri) of said a given number of vertices (Rik) comprising: in said set (R), selecting subsets (Ri, Rj), called pre-selected subsets, such that a tree (Ti, Tj) is associated respectively to said subset (Ri, Rj), said associated trees (Ti, Tj) being pairwise disjoint and constructing (301) each tree (Ti); associating a weight to each said tree (Ti); choosing the subset for which the tree (Ti) has the highest weight.Type: ApplicationFiled: March 15, 2023Publication date: September 21, 2023Applicant: BULL SASInventors: Arnaud GAZDA, Simon MARTIEL, Jon OILLARBURU
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Patent number: 11669764Abstract: A method for the development of a compilation process for a quantum circuit on a quantum processor, includes an implementation step of the compilation method including an iteration loop successively including: a step of simulation of a given implementation of the logical qubits on the physical qubits of the quantum processor; a step of detecting, in the quantum circuit, ineffective quantum gate(s); a step of estimating the number of quantum swap gates to be inserted into the quantum circuit so that all of the quantum gates of the quantum circuit are effective; and a retroaction step, by way of a simulated annealing, involving a new step of simulation, until attaining, whereupon all the quantum gates are effective: either a minimum threshold of the number of estimated quantum value swap gates between two physical qubits, or a maximum threshold of iterations in the loop.Type: GrantFiled: December 26, 2019Date of Patent: June 6, 2023Assignee: BULL SASInventors: Arnaud Gazda, Simon Martiel
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Publication number: 20230084876Abstract: The present disclosure relates to a computing system for executing hybrid programs, said computing system comprising: hardware resources comprising quantum computing resources and classical computing resources, said quantum computing resources comprising one or more quantum computers; software resources to be executed on the hardware resources; wherein the software resources comprise a plurality of processing modules comprising interfaces of two possible types referred to as upstream interface and downstream interface, wherein said plurality of processing modules comprises: at least one quantum processing module for each quantum computer, wherein each quantum processing module comprises an upstream interface; a plurality of plugin modules, wherein each plugin module comprises both an upstream interface and a downstream interface; wherein a hybrid program is built by connecting at least one plugin module and one quantum processing module.Type: ApplicationFiled: September 8, 2022Publication date: March 16, 2023Applicant: BULL SASInventors: Cyril ALLOUCHE, Thomas AYRAL, Simon MARTIEL, Arnaud GAZDA
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Patent number: 11379197Abstract: Examples include quantum computing compiling methods comprising considering a threshold corresponding to a maximum number of qubits available for processing in any one subsystem of a plurality of interconnected qubit subsystems and identifying a total number of qubits submitted to a specific quantum circuit, the total number of qubits exceeding the threshold. The methods comprise compiling a first section of the specific quantum circuit on a first subsystem by successively selecting quantum gates. If a selected quantum gate is to be applied to qubits assigned to different subsystems, the passing of a qubit from the first subsystem to a second subsystem through a junction connecting the first subsystem to the second subsystem is coded, and the second section of the specific quantum circuit is compiled on the second subsystem.Type: GrantFiled: March 11, 2021Date of Patent: July 5, 2022Assignee: BULL SASInventors: Arnaud Gazda, Simon Martiel
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Patent number: 11379196Abstract: Examples relate to a quantum computing compiling method that includes ordering quantum gates of a nearest neighbor quantum circuit in function of dependencies between the quantum gates to obtain a quantum gates hierarchical order. The hierarchical order includes a succession of front lines comprising multiple respective quantum gates of the nearest neighbor quantum circuit. The method includes successively selecting, for each front line, and following the hierarchical order, a shuttling for each respective quantum gate of the front line. The shuttling selection is, for each front line, based on a predefined constraint.Type: GrantFiled: December 18, 2020Date of Patent: July 5, 2022Assignee: BULL SASInventors: Arnaud Gazda, Simon Martiel
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Publication number: 20210286599Abstract: Examples include quantum computing compiling methods comprising considering a threshold corresponding to a maximum number of qubits available for processing in any one subsystem of a plurality of interconnected qubit subsystems and identifying a total number of qubits submitted to a specific quantum circuit, the total number of qubits exceeding the threshold. The methods comprise compiling a first section of the specific quantum circuit on a first subsystem by successively selecting quantum gates. If a selected quantum gate is to be applied to qubits assigned to different subsystems, the passing of a qubit from the first subsystem to a second subsystem through a junction connecting the first subsystem to the second subsystem is coded, and the second section of the specific quantum circuit is compiled on the second subsystem.Type: ApplicationFiled: March 11, 2021Publication date: September 16, 2021Applicant: BULL SASInventors: Arnaud GAZDA, Simon MARTIEL
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Publication number: 20210191698Abstract: Examples relate to a quantum computing compiling method that includes ordering quantum gates of a nearest neighbor quantum circuit in function of dependencies between the quantum gates to obtain a quantum gates hierarchical order. The hierarchical order includes a succession of front lines comprising multiple respective quantum gates of the nearest neighbor quantum circuit. The method includes successively selecting, for each front line, and following the hierarchical order, a shuttling for each respective quantum gate of the front line. The shuttling selection is, for each front line, based on a predefined constraint.Type: ApplicationFiled: December 18, 2020Publication date: June 24, 2021Inventors: Arnaud GAZDA, Simon MARTIEL
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Patent number: 11042685Abstract: A method for developing a method for compiling a quantum circuit on a quantum processor, comprising: a selection step: of a quantum circuit, of a quantum processor whereupon to compile the quantum circuit, of a set of quantum gates that can be executed on the selected quantum processor, of a metric, a meta-heuristic, a step of division of the selected quantum circuit into quantum sub-circuits, a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor to comprise only quantum gates that can be executed by the selected quantum processor, a second step of re-writing of the quantum sub-circuits, by the selected meta-heuristic, to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving the selected metric, a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.Type: GrantFiled: December 26, 2019Date of Patent: June 22, 2021Assignee: BULL SASInventors: Simon Martiel, Arnaud Gazda
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Publication number: 20200218847Abstract: A method for developing a method for compiling a quantum circuit on a quantum processor, comprising: a selection step: of a quantum circuit, of a quantum processor whereupon to compile the quantum circuit, of a set of quantum gates that can be executed on the selected quantum processor, of a metric, a meta-heuristic, a step of division of the selected quantum circuit into quantum sub-circuits, a first step of re-writing of the quantum sub-circuits comprising quantum gates that cannot be executed by the selected quantum processor to comprise only quantum gates that can be executed by the selected quantum processor, a second step of re-writing of the quantum sub-circuits, by the selected meta-heuristic, to obtain quantum sub-circuits comprising quantum gates that can be executed by the selected quantum processor, improving the selected metric, a step of regrouping of the quantum sub-circuits in a quantum circuit compilable by the selected quantum processor.Type: ApplicationFiled: December 26, 2019Publication date: July 9, 2020Inventors: Simon MARTIEL, Arnaud GAZDA
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Publication number: 20200219003Abstract: A method for the development of a compilation process for a quantum circuit on a quantum processor, comprises: an implementation step of the compilation method comprising: an iteration loop successively comprising: a step of simulation of a given implementation of the logical qubits on the physical qubits of the quantum processor, a step of detecting, in the quantum circuit, ineffective quantum gate(s), a step of estimating the number of quantum swap gates to be inserted into the quantum circuit so that all of the quantum gates of the quantum circuit are effective, a retroaction step, by means of a simulated annealing, involving a new step of simulation, until attaining, whereupon all the quantum gates are effective: either a minimum threshold of the number of estimated quantum value swap gates between two physical qubits, or a maximum threshold of iterations in the loop.Type: ApplicationFiled: December 26, 2019Publication date: July 9, 2020Inventors: Arnaud GAZDA, Simon MARTIEL