Abstract: A method and apparatus of temperature compensation for an integrated circuit using on-chip circuits, sensors, and an algorithm. The chip includes an on-chip reference circuit, an on-chip sensor measuring a parameter relative to the reference, and an on-chip computation means for processing an algorithm. A supplemental off-chip reference circuit is also used. The algorithm carries out the following steps: (A) performing a first calibration of an internal reference residing in an integrated circuit system on-chip at a first (higher) temperature at a first testing site, and (B) utilizing calibration data obtained at the step (A) to perform a second calibration of the internal reference source residing on the integrated system on-chip at a second (lower) temperature at a second testing site.

Abstract: A current sensing analog to digital converter (CS-ADC) is disclosed. The current sensing analog to digital converter comprises a modulator adapted to sense a change in current and generate an oversampled signal. The converter further includes a decimation filter system coupled to modulator for removing out of band noise from the signal and reduce the data rate to achieve a high resolution signal. A current sensing analog to digital converter (CS-ADC) is disclosed that samples the charge or discharge current flowing through an external sense resistor RSENSE. The sample from the RSENSE is processed by a delta-sigma modulator which generates an over sampled noise shaped signal. From this signal a decimation filter system removes the out-of band noise and reduces the data rate to achieve a high-resolution signal. The CS-ADC also provides regular current detection. The regular current detection compares the data from conversion against charge/discharge threshold levels specified by the user.

Abstract: Apparatus, method and computer program product are provided for battery management. In one implementation, a method is provided. The method includes enabling determining if a charger is coupled to a battery system. The battery system includes one more cells and a charge enable transistor. The method also includes substantially fully enabling the charge enable transistor including driving a charge enable transistor gate terminal at a potential that is substantially greater than a potential of the cells.

Abstract: A battery pack can include one or more battery cells, current blocking transistors and a battery management system. The disclosed implementations handle over-currents drawn from the battery cells that cause unstable operation of the battery management system. The over-currents are handled without causing an undesired drop in voltage output from the battery cells. The disclosed implementations can handle over-currents even if the over-currents cause the battery management system supply voltage to drop below a minimum operating voltage level for a certain period of time. The disclosed implementations use current blocking transistors that can be configured to block current flow and ensure safe operation of the battery cells in cases where the current drawn from the battery cells would be sufficiently high for a sufficiently long period of time to cause damage to the battery cells.

Abstract: Apparatus, method and computer program product are provided for battery management. In one implementation, a method of communication provided. The method includes enabling determining when a battery pack is coupled to a device, the battery pack including a battery management system. The method also includes generating a random number at the battery management system, the battery management system including battery monitoring circuitry, a processor, memory and a random number generator. The method includes using the random number to provide authentication and if authentication succeeds, enabling communication between the battery pack and the device.

Abstract: In one implementation, a method for charging a battery system is provided. The method includes enabling determining if a charger is coupled to a battery system, the battery system including one or more cells and a charge enable transistor. The method also includes enabling determining if a voltage level of the cells is less than a predetermined first low voltage level. If the voltage level of the cells is less than the predetermined first low voltage level, enabling charging of the cells at a reduced rate including adjusting a voltage applied to the charge transistor gate terminal to regulate a voltage seen by the charger to a level that is less than a predetermined second voltage level. Additionally, when the voltage of the cells reaches the predetermined first low voltage level, the method includes substantially fully enabling the charge transistor to allow for charging at full rate by the charger.

Abstract: A current sensing analog to digital converter (CS-ADC) is disclosed. The current sensing analog to digital converter comprises a modulator adapted to sense a change in current and generate an oversampled signal. The converter further includes a decimation filter system coupled to modulator for removing out of band noise from the signal and reduce the data rate to achieve a high resolution signal. A current sensing analog to digital converter (CS-ADC) is disclosed that samples the charge or discharge current flowing through an external sense resistor RSENSE. The sample from the RSENSE is processed by a delta-sigma modulator which generates an over sampled noise shaped signal. From this signal a decimation filter system removes the out-of band noise and reduces the data rate to achieve a high-resolution signal. The CS-ADC also provides regular current detection. The regular current detection compares the data from conversion against charge/discharge threshold levels specified by the user.

Abstract: A current sensing analog to digital converter (CS-ADC) is disclosed. The current sensing analog to digital converter comprises a modulator adapted to sense a change in current and generate an oversampled signal. The converter further includes a decimation filter system coupled to modulator for removing out of band noise from the signal and reduce the data rate to achieve a high resolution signal. A current sensing analog to digital converter (CS-ADC) is disclosed that samples the charge or discharge current flowing through an external sense resistor RSENSE. The sample from the RSENSE is processed by a delta-sigma modulator which generates an over sampled noise shaped signal. From this signal a decimation filter system removes the out-of band noise and reduces the data rate to achieve a high-resolution signal. The CS-ADC also provides regular current detection. The regular current detection compares the data from conversion against charge/discharge threshold levels specified by the user.

Abstract: A microcontroller is disclosed. The microcontroller comprises a processor system and a high voltage interface coupled to the processor system and adapted to be coupled to a battery. The microcontroller further includes a battery management system for monitoring the battery and managing the battery based upon the monitoring of the battery. The microcontroller is a single chip. This one-chip solution saves design cost and PCB space in addition to broadening the functionality of the smart battery application. With the accuracy of the microcontroller, the charge status of the battery can be predicted more accurately and therefore effectively increases actual battery capacity.

Abstract: A current sensing analog to digital converter (CS-ADC) is disclosed. The current sensing analog to digital converter comprises a modulator adapted to sense a change in current and generate an oversampled signal. The converter further includes a decimation filter system coupled to modulator for removing out of band noise from the signal and reduce the data rate to achieve a high resolution signal. A current sensing analog to digital converter (CS-ADC) is disclosed that samples the charge or discharge current flowing through an external sense resistor RSENSE. The sample from the RSENSE is processed by a delta-sigma modulator which generates an over sampled noise shaped signal. From this signal a decimation filter system removes the out-of band noise and reduces the data rate to achieve a high-resolution signal. The CS-ADC also provides regular current detection. The regular current detection compares the data from conversion against charge/discharge threshold levels specified by the user.

Abstract: A method and apparatus of temperature compensation for an integrated circuit using on-chip circuits, sensors, and an algorithm. The chip includes an on-chip reference circuit, an on-chip sensor measuring a parameter relative to the reference, and an on-chip computation means for processing an algorithm. A supplemental off-chip reference circuit is also used. The algorithm carries out the following steps: (A) performing a first calibration of an internal reference residing in an integrated circuit system on-chip at a first (higher) temperature at a first testing site, and (B) utilizing calibration data obtained at the step (A) to perform a second calibration of the internal reference source residing on the integrated system on-chip at a second (lower) temperature at a second testing site.