Patents by Inventor Arne S. Barras

Arne S. Barras has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7979816
    Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.
    Type: Grant
    Filed: April 9, 2008
    Date of Patent: July 12, 2011
    Assignee: Xilinx, Inc.
    Inventors: Arne S. Barras, Rajeev Jayaraman
  • Patent number: 7380219
    Abstract: Method and apparatus for implementing a circuit design for an integrated circuit is described. In one example, a first version of the circuit design is processed (408) with at least one design tool. Statistical data is captured (410) for the at least one design tool and operational attributes thereof are automatically adjusted (420) in response to the statistical data. A second version of the circuit design is processed (422) with the at least one design tool having the adjusted operational attributes. In another example, the circuit design is processed (506) with at least one design tool in a first iteration. Statistical data is captured (508) for the at least one design tool and operational attributes thereof are automatically adjusted (514) for a second iteration in response to the statistical data of the first iteration. The circuit design is re-processed (516) with the at least one design tool having the adjusted operational attributes in the second iteration.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: May 27, 2008
    Assignee: Xilinx, Inc.
    Inventors: Arne S. Barras, Rajeev Jayaraman
  • Patent number: 7086029
    Abstract: Method and apparatus for incremental design is described. More particularly, a text-circuit description of the integrated circuit having logic groups of respective logic instances is obtained. Area groups are created for the logic groups and correspondingly assigned. Unchanged logic groups are guided on an incremental implementation from existing guide files, and changed logic groups are re-implemented in area groups corresponding to the changed logic groups. In this manner, runtime of the unchanged logic groups is reduced by an incremental guide implementation instead of a re-implementation, while performance of such unchanged logic groups is maintained from a prior implementation. Furthermore, degrees of freedom for re-implementing are enhanced for improving a design, as all prior mapping, placing and routing within a changed area group may be stripped for re-implementation.
    Type: Grant
    Filed: February 18, 2003
    Date of Patent: August 1, 2006
    Assignee: Xilinx, Inc.
    Inventors: Arne S. Barras, Jeffrey M. Mason, Kate L. Kelley