Patents by Inventor ARNE WANVIK VENAS
ARNE WANVIK VENAS has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220335168Abstract: A handshake circuit portion for performing a handshake procedure to facilitate data reception by an associated circuit portion is provided. The handshake circuit portion comprises a request signal input for detecting a request signal from a further handshake circuit portion associated with a further circuit portion, an acknowledge signal output for asserting an acknowledge signal for the further handshake circuit portion, and a blocking signal input for detecting a blocking signal from the associated circuit portion. The handshake circuit portion is arranged to detect a request signal via the request signal input, determine if a blocking signal is present on the blocking signal input, and if a blocking signal is not present on the blocking signal input, respond to the request signal by asserting an acknowledge signal via the acknowledge signal output.Type: ApplicationFiled: April 11, 2022Publication date: October 20, 2022Applicant: Nordic Semiconductor ASAInventors: Arne Wanvik Venås, Karianne Krokan Kragseth, Per-Carsten Skoglund, Steffen Eidal Wiken, Vegard Endresen
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Patent number: 11372461Abstract: An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.Type: GrantFiled: April 22, 2021Date of Patent: June 28, 2022Assignee: Nordic Semiconductor ASAInventors: Ari Oja, Åsmund Holen, Arne Wanvik Venås, Knut Austbø, Ragnar Haugen
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Publication number: 20210333852Abstract: An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.Type: ApplicationFiled: April 22, 2021Publication date: October 28, 2021Applicant: Nordic Semiconductor ASAInventors: Ari Oja, Åsmund Holen, Arne Wanvik Venås, Knut Austbø, Ragnar Haugen
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Patent number: 10114407Abstract: A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).Type: GrantFiled: June 20, 2013Date of Patent: October 30, 2018Assignee: NORDIC SEMICONDUCTOR ASAInventors: Markus Bakka Hjerto, Arne Wanvik Venas
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Patent number: 10055193Abstract: An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).Type: GrantFiled: June 20, 2013Date of Patent: August 21, 2018Assignee: NORDIC SEMICONDUCTOR ASAInventors: Per Carsten Skoglund, Asghar Havashki, Arne Wanvik Venas, Asmund Holen, Markus Bakka Hjerto
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Patent number: 9197211Abstract: A digital circuit portion comprises a flip-flop (20) having a clock input (22) and an output (data); a clock signal (ck); and a gate (24) between said clock signal (ck) and said clock input (22), said gate (24) being arranged selectively to couple the clock signal (ck) to the clock input (22) in dependence upon the output of the flip-flop (20).Type: GrantFiled: July 21, 2014Date of Patent: November 24, 2015Assignee: NORDIC SEMICONDUCTOR ASAInventor: Arne Wanvik Venas
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Publication number: 20150186113Abstract: An arrangement for transferring a data signal (data_a) from a first clock domain (2) to a second clock domain (4) in a digital system. The arrangement has a signal input (6, 7) for receiving an input signal (data_a) from the first clock domain (2), means (6, 7) for storing the input signal (data_a), and means (12, 13) for transferring the input signal (data_a) to the second clock domain (4) following a transition in the clock signal (ck) of the second clock domain (4).Type: ApplicationFiled: June 20, 2013Publication date: July 2, 2015Applicant: NORDIC SEMICONDUCTOR ASAInventors: Per Carsten Skoglund, Asghar Havashki, Arne Wanvik Venas, Asmund Holen, Markus Bakka Hjerto
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Publication number: 20150177776Abstract: A system (1) for transferring a data signal (sig_fast) from a first clock domain (4) to a second clock domain (8). The first clock domain (4) has a first clock (ck_fast) with a frequency greater than the frequency of a second clock (ck_slow) in the second clock domain (8). The system (1) also has a signal input (10) for receiving an input signal (sig_fast) from the first clock domain (4), means (16, 18) for checking whether the second clock (ck_slow) is in a part of its cycle away from a forthcoming transition, and means (22) for transferring the input signal (sig_fast) to the second clock domain (8) if the checking means (16, 18) determines that the second clock (ck_slow) is in part of its cycle away from a forthcoming transition. The checking means (16, 18) are clocked by the first clock (ck_fast).Type: ApplicationFiled: June 13, 2013Publication date: June 25, 2015Applicant: NORDIC SEMICONDUCTOR ASAInventors: Markus Bakka Hjerto, Arne Wanvik Venas
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Publication number: 20150022252Abstract: A digital circuit portion comprises a flip-flop (20) having a clock input (22) and an output (data); a clock signal (ck); and a gate (24) between said clock signal (ck) and said clock input (22), said gate (24) being arranged selectively to couple the clock signal (ck) to the clock input (22) in dependence upon the output of the flip-flop (20).Type: ApplicationFiled: July 21, 2014Publication date: January 22, 2015Applicant: NORDIC SEMICONDUCTOR ASAInventor: ARNE WANVIK VENAS