Patents by Inventor Arnel Senosa Trasporto

Arnel Senosa Trasporto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130154105
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing routable traces including a first routable trace with a top plate and a second routable trace; mounting an integrated circuit partially over a second routable trace; forming an encapsulation over and around the first routable trace and the integrated circuit; forming a hole through the encapsulation to the top plate; and forming a protective coat directly on the encapsulation with the first routable trace between and in contact with the protective coat and the encapsulation.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154080
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154119
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead having a lead top side; forming a lower interior conductive layer directly on the lead top side; forming an interior insulation layer directly on the lower interior conductive layer; forming an upper interior conductive layer directly on the interior insulation layer; and mounting an integrated circuit over the upper interior conductive layer.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130154120
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead; forming an interior conductive layer directly on the peripheral lead; forming a vertical connector directly on the interior conductive layer, the vertical connector having a connector top side; connecting an integrated circuit to the interior conductive layer; and forming an encapsulation over the integrated circuit, the encapsulation having an encapsulation top side coplanar with the connector top side.
    Type: Application
    Filed: December 15, 2011
    Publication date: June 20, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130099367
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a partially removed portion including: a conductive pattern having a lower surface on a top frame surface of the leadframe, a contact protrusion and a support lead on the lower surface of the conductive pattern, the support lead for supporting the partially removed portion of the leadframe during an encapsulation process, and a contact pad on a bottom surface of the contact protrusion; mounting an integrated circuit die above the conductive pattern; applying an encapsulation on the integrated circuit die and the conductive pattern, the lower surface of the conductive pattern exposed from the encapsulation; and removing at least a portion of the leadframe to form a contact lead and expose a bottom surface of the encapsulation.
    Type: Application
    Filed: June 19, 2012
    Publication date: April 25, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Emmanuel Espiritu
  • Publication number: 20130099365
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe with a grid lead and a support pad; connecting a redistribution layer to the grid lead, the redistribution layer over the support pad; mounting an integrated circuit over the redistribution layer; applying an encapsulation on the redistribution layer, the redistribution layer in an interior area of the leadframe and the interior area under the integrated circuit; forming a support pad residue on the bottom surface of the redistribution layer by removing the support pad under the encapsulation and the interior redistribution layer; and forming an insulation layer on the support pad residue and the grid lead.
    Type: Application
    Filed: March 22, 2012
    Publication date: April 25, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20130087902
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a thermal attach cluster includes: forming a heat collector having a heat dissipation surface, forming a cluster bridge, having a thermal surface, connected to the heat collector, forming a cluster pad, having an attachment surface, connected to the end of the cluster bridge opposite the heat collector; connecting an integrated circuit to the thermal attach cluster; and forming an encapsulation over the thermal attach cluster with the heat dissipation surface, the thermal surface, and the attachment surface exposed from and coplanar with the encapsulation.
    Type: Application
    Filed: June 20, 2012
    Publication date: April 11, 2013
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Wei Chun Ang
  • Patent number: 8399991
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: March 19, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Publication number: 20120326284
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead array having an innermost space with an innermost lead having an inner lead profile different around an inner non-horizontal side of the innermost lead; forming a middle lead having a middle lead profile the same around a lead side of the middle lead; placing an integrated circuit in the innermost space adjacent to the innermost lead; and forming a package encapsulation over the integrated circuit, the innermost lead, and the middle lead.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 27, 2012
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20120286400
    Abstract: A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.
    Type: Application
    Filed: July 23, 2012
    Publication date: November 15, 2012
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Publication number: 20120280407
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20120280390
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a top with a depression; applying a dielectric material in the depression, the dielectric material having a gap formed therein and exposing a portion of the top therefrom; forming a trace within the gap and in direct contact with the top, the trace extending laterally over an upper surface of the dielectric material; and connecting an integrated circuit to the terminal through the trace.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Zigmund Ramirez Camacho
  • Publication number: 20120280377
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a first top distribution layer on the peripheral lead top side, the first top distribution layer having a first top terminal; connecting an integrated circuit to the first top distribution layer, the integrated circuit having a central portion directly over a plurality of the first top terminal; and applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20120280408
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a die paddle having an internal portion with a trench along a perimeter of the die paddle; forming an interconnect having a concave indentation and an upper portion, the upper portion, opposite the concave indentation, aligned horizontally to the internal portion; attaching an integrated circuit device on the die paddle, the trench between the integrated circuit device and the perimeter; attaching an electrical connector to the integrated circuit device and to the upper portion; and applying an encapsulation over the integrated circuit device, the electrical connector, the die paddle, and the interconnect, the concave indentation exposed below the encapsulation.
    Type: Application
    Filed: May 5, 2011
    Publication date: November 8, 2012
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20120280376
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a peripheral lead having a peripheral lead bottom side, a peripheral lead top side, a peripheral lead non-horizontal side, a peripheral lead horizontal ridge, and a peripheral lead conductive plate, the peripheral lead horizontal ridge protruding from the peripheral lead non-horizontal side; forming a central lead adjacent to the peripheral lead; forming a first top distribution layer on the peripheral lead top side; connecting an integrated circuit to the first top distribution layer; applying an insulation layer directly on a bottom extent of the first top distribution layer and a peripheral lead ridge lower side of the peripheral lead horizontal ridge; and attaching a heatsink to the central lead under the integrated circuit.
    Type: Application
    Filed: March 21, 2012
    Publication date: November 8, 2012
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 8269324
    Abstract: An integrated circuit package system includes: providing a lead having a lead connection surface for connectivity to a next level system; attaching an integrated circuit over the lead having the lead connection surface substantially within a region below a perimeter of the integrated circuit without a die paddle, a substrate conductor, or a redistribution layer; and attaching a die connector to the integrated circuit and the lead.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Arnel Senosa Trasporto, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Jose Alvin Caparas
  • Patent number: 8252666
    Abstract: A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.
    Type: Grant
    Filed: August 18, 2010
    Date of Patent: August 28, 2012
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry Descalzo Bathan, Zigmund Ramirez Camacho, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Publication number: 20120205811
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a terminal having a cornered dimple formed therein as a simple concave polygon; mounting an integrated circuit above and coupled to the terminal; and forming an encapsulation encapsulating the integrated circuit and portions of the terminal.
    Type: Application
    Filed: February 6, 2012
    Publication date: August 16, 2012
    Inventors: Byung Tai Do, Linda Pei Ee Chua, Arnel Senosa Trasporto
  • Publication number: 20120146192
    Abstract: A method of manufacture of an integrated circuit mounting system includes: providing a die paddle with a component side having a die mount area and a recess with more than one geometric shape; applying an adhesive on the die mount area and in a portion of the recess; and mounting an integrated circuit device with an inactive side directly on the adhesive.
    Type: Application
    Filed: December 14, 2010
    Publication date: June 14, 2012
    Inventors: Byung Joon Han, Byung Tai Do, Arnel Senosa Trasporto, Henry Descalzo Bathan
  • Publication number: 20120074547
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a package paddle; forming a lead adjacent the package paddle, the lead having a hole in a lead body top side and a lead ridge protruding from a lead non-horizontal side; mounting an integrated circuit over the package paddle; connecting an electrical connector to the lead and the integrated circuit; and forming a fill layer within the hole.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Byung Tai Do, Reza Argenty Pagaila, Linda Pei Ee Chua, Arnel Senosa Trasporto