Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: Aspects of the disclosure relate to a processor core including an execution unit and a usage ratio controller. The execution unit is operable for executing a command forwarded to the execution unit. The usage ratio controller is operatively coupled with the execution unit. The usage ratio controller is operable for controlling a usage ratio of the execution unit. The usage ratio corresponds to the fraction of an observation time during which the execution unit is executing commands of an application. Other aspects of the disclosure relate to a method for detecting or analyzing a bottleneck in a processor core for a given application. The method includes controlling a usage ratio of at least one execution unit of the processor core and measuring the resulting application performance.

Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: A method to determine an oldest instruction in an instruction queue of a processor with multiple instruction threads, wherein each of the multiple instruction threads have a unique thread identifier. The method includes tagging each instruction thread, of the multiple instruction threads, in the instruction queue with a unique tag number according to a round-robin scheme, wherein the unique tag number includes the unique thread identifier for each instruction thread and a round number in the round-robin scheme. The method further includes selecting, for each instruction thread, of the multiple instruction threads, the instruction thread with a lowest tag number from the multiple instruction threads in the instruction queue that are tagged with an oldest round number from the round-robin scheme.

Abstract: Aspects of the disclosure relate to a processor core including an execution unit and a usage ratio controller. The execution unit is operable for executing a command forwarded to the execution unit. The usage ratio controller is operatively coupled with the execution unit. The usage ratio controller is operable for controlling a usage ratio of the execution unit. The usage ratio corresponds to the fraction of an observation time during which the execution unit is executing commands of an application. Other aspects of the disclosure relate to a method for detecting or analyzing a bottleneck in a processor core for a given application. The method includes controlling a usage ratio of at least one execution unit of the processor core and measuring the resulting application performance.

Abstract: A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.

Abstract: A method to determine an oldest instruction in an instruction queue of a processor with multiple instruction threads, wherein each of the multiple instruction threads have a unique thread identifier. The method includes tagging each instruction thread, of the multiple instruction threads, in the instruction queue with a unique tag number according to a round-robin scheme, wherein the unique tag number includes the unique thread identifier for each instruction thread and a round number in the round-robin scheme. The method further includes selecting, for each instruction thread, of the multiple instruction threads, the instruction thread with a lowest tag number from the multiple instruction threads in the instruction queue that are tagged with an oldest round number from the round-robin scheme.

Abstract: A buffer is configured to store a plurality of last addresses accessed by a processor core from a memory. A minimum distance extraction circuit determines distances of a current memory address accessed by the processor core from each of the plurality of last addresses in the buffer and determines a minimum distance from the distances. A limit determination circuit compares the minimum distance to each of a plurality of ranges of distances and selects a range of the plurality of ranges within which the minimum distance falls. Each of a plurality of counters of a counter circuit is associated with a corresponding one of the plurality of ranges. A counter of the plurality of counters is to be incremented corresponding to the selected range.

Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals.

Abstract: Systems, devices, and methods are provided that enable the revision of RF command handling software stored in ROM, and that enable to supplementation of RF command handling software stored in ROM. Examples of the systems, devices, and methods make use of a lookup data structure stored within writable non-volatile memory.

Abstract: A method of providing multiple clock frequencies for an integrated circuit having a plurality of modules. A reference clock signal (fin) is frequency division processed to generate sub-divider outputs of fin divided by a plurality of different (i) prime numbers and (ii) prime numbers raised to an integer power to collectively provide a plurality of prime number-based clock signals that each have a frequency divider factor (divider factor) in a predetermined divider range. For at least a portion of other divider factors, two or more of the sub-divider outputs are combined to generate additional clock signals that each provide an additional divider factor. A first module frequency selects at least a first selected clock signal from the prime number-based clock signals and additional clock signals, and a second module frequency selects at least a second selected clock signal from the prime number-based clock signals and additional clock signals.

Abstract: An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error.

Abstract: An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES) has a first data processing channel having a first processing stage for performing encryption and decryption of data blocks of a predefined length, and a second data processing channel having a second processing stage for performing encryption and decryption of data blocks. The electronic device also has a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage, and to control the second processing stage to compute a message authentication code over the encrypted or decrypted message received from the first processing stage block-by-block.

Abstract: An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error.

Abstract: An electronic device for encrypting and decrypting data blocks of a message having n data blocks in accordance with the data encryption standard (DES) is provided. The electronic device has a first data processing channel having a first processing stage for performing encryption and decryption of data blocks of a predefined length, and a first input data buffer coupled to a data input and to the first processing stage, and a second data processing channel having a second processing stage for performing encryption and decryption of data blocks, a second data input buffer coupled to an output of the first processing stage and to the second processing stage. The electronic device also has a control stage (FSM) for controlling the first processing stage and the second processing stage, so as to perform an encryption or decryption step with the second processing stage on an encrypted/decrypted data block output from the first processing stage.

Abstract: An ankle-foot orthosis including a footplate having a line of progression that extends from a heel portion to a middle portion to a toe portion of the footplate, and a leg support connected to the footplate. The footplate has at least two superimposed and discrete structural layers each having a different length and extending along at least a segment of a length of the footplate. The footplate defines regions with different thicknesses and stiffness. The leg support has a first end portion connected to the heel portion of the footplate.