Abstract: A method and device for cleaning an electrical contact. Semiconductor testing device. Process of manufacturing integrated circuits. The electrical contact is used for contacting an integrated circuit and accumulates debris during use. The method comprises directing electromagnetic radiation at the contact. The electromagnetic energy reacts with at least one of the contact and the debris so as to cause at least a portion of the debris on the contact to be removed. The electromagnetic radiation may comprise coherent radiation, such as electromagnetic radiation generated using a laser. The portion of the debris may comprise organic debris, aluminum oxide, polyimide, or other debris. According to one aspect of the invention, the contact comprises a conductive material and the electromagnetic radiation causes removal of the portion of the debris substantially without removal of the conductive material.

Abstract: A method and device for cleaning an electrical contact. Semiconductor testing device. Process of manufacturing integrated circuits. The electrical contact is used for contacting an integrated circuit and accumulates debris during use. The method comprises directing electromagnetic radiation at the contact. The electromagnetic energy reacts with at least one of the contact and the debris so as to cause at least a portion of the debris on the contact to be removed. The electromagnetic radiation may comprise coherent radiation, such as electromagnetic radiation generated using a laser. The portion of the debris may comprise organic debris, aluminum oxide, polyimide, or other debris. According to one aspect of the invention, the contact comprises a conductive material and the electromagnetic radiation causes removal of the portion of the debris substantially without removal of the conductive material.

Abstract: Test jig apparatus for testing an integrated circuit chip that suppresses build-up and subsequent discharge of electrical charge on the test jig apparatus or on the chip. The test jig apparatus includes a base of selected material having a top surface of the same general shape and dimensions as the chip to be tested. Preferably, the entire top surface of the base is electrically grounded. The base has two or more side surfaces with side surface planes that are approximately perpendicular to a plane defining the top surface of the base. Each side surface accepts a side plate, made of a selected material such as ULTIM, that can be attached to or removed from the base. The side plate material resists electrical charge buildup and subsequent discharge so that the chip being tested is not subjected to electrical discharge from this source. In another embodiment, the side plates are replaced by plates mounted on the top surface of the base.