Patents by Inventor Arno Zechmann

Arno Zechmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10903120
    Abstract: A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: January 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Publication number: 20190259874
    Abstract: In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Paul Ganitzer, Arno Zechmann, Michael Jacob
  • Patent number: 10256149
    Abstract: A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Publication number: 20190043757
    Abstract: A method includes providing a semiconductor base substrate having a substantially planar growth surface and one or more preferred crystallographic cleavage planes and an epitaxial first type III-V semiconductor layer on the planar growth surface. A first trench that vertically extends from an upper surface of the first type III-V semiconductor layer is formed at least to the planar growth surface. The first trench has a first trench length direction that is antiparallel to the one or more preferred crystallographic cleavage planes.
    Type: Application
    Filed: September 28, 2018
    Publication date: February 7, 2019
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Publication number: 20180247869
    Abstract: A semiconductor base substrate having a substantially planar growth surface is provided. A first type III-V semiconductor layer is epitaxially grown on the growth surface. First and second trenches that vertically extend from an upper surface of the first type III-V semiconductor layer at least to the growth surface are formed. The first and second trenches are filled with a filler material that is different from material of the type III-V semiconductor layer. A cut that separates the first type III-V semiconductor layer and the base substrate into two discrete semiconductor chips is formed. The cut is formed in a lateral section of the first type III-V semiconductor layer that is between the first and second trenches.
    Type: Application
    Filed: February 28, 2017
    Publication date: August 30, 2018
    Inventors: Arno Zechmann, Gianmauro Pozzovivo
  • Publication number: 20170170282
    Abstract: In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Arno Zechmann, Annette Saenger, Ulrike Fastner, Beate Weissnicht, Stefan Krivec
  • Patent number: 9660037
    Abstract: In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: May 23, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Arno Zechmann, Annette Sanger, Ulrike Fastner, Beate Weissnicht, Stefan Krivec
  • Publication number: 20160336272
    Abstract: A semiconductor device includes a semiconductor substrate having first and second terminals of one or more semiconductor devices, first and second barrier metal regions electrically connected to the first and second terminals, respectively, and first and second gold metallization structures electrically connected to the first and second terminals via the first and second barrier metal regions, respectively. The first and second gold metallization structures contain diffused copper atoms. Interfaces between the first and second barrier metals and the first and second gold metallization structures, respectively, are substantially devoid of metallic copper.
    Type: Application
    Filed: July 26, 2016
    Publication date: November 17, 2016
    Inventor: Arno Zechmann
  • Patent number: 9425090
    Abstract: An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is formed on the barrier layer. The seed includes a noble metal other than gold. The substrate is masked so that a first mask opening is laterally aligned with the first terminal. An unmasked portion of the seed layer is electroplated using a gold electrolyte solution so as to form a first gold metallization structure in the first mask opening. The mask, the masked portions of the seed layer, and the barrier layer are removed. The noble metal from the unmasked portion of the seed layer is diffused into the first gold metallization structure. The first gold metallization structure is electrically connected to the first terminal via the barrier layer.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 23, 2016
    Assignee: Infineon Technologies Austria AG
    Inventor: Arno Zechmann
  • Publication number: 20160086847
    Abstract: An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is formed on the barrier layer. The seed includes a noble metal other than gold. The substrate is masked so that a first mask opening is laterally aligned with the first terminal. An unmasked portion of the seed layer is electroplated using a gold electrolyte solution so as to form a first gold metallization structure in the first mask opening. The mask, the masked portions of the seed layer, and the barrier layer are removed. The noble metal from the unmasked portion of the seed layer is diffused into the first gold metallization structure. The first gold metallization structure is electrically connected to the first terminal via the barrier layer.
    Type: Application
    Filed: September 19, 2014
    Publication date: March 24, 2016
    Inventor: Arno Zechmann
  • Publication number: 20150221764
    Abstract: In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.
    Type: Application
    Filed: February 4, 2014
    Publication date: August 6, 2015
    Applicant: Infineon Technologies AG
    Inventors: Paul Ganitzer, Arno Zechmann, Michael Jacob
  • Patent number: 8502274
    Abstract: Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Thomas Detzel, Michael Nelhiebel, Arno Zechmann, Stefan Decker, Robert Illing, Sven Gustav Lanzerstorfer, Christian Djelassi, Bernhard Auer, Stefan Woehlert