Abstract: Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed.

Abstract: Methods and apparatus for front-to-back alignment using narrow scribe lines are disclosed. An apparatus is disclosed that includes a semiconductor wafer comprising a plurality of areas for the fabrication of integrated circuit devices on a device side, the integrated circuit devices arranged in rows and columns and spaced from one another by a plurality of scribe lines disposed on the semiconductor wafer in areas between the integrated circuit devices and free from integrated circuit devices; and one or more alignment marks disposed on the semiconductor wafer, the alignment marks positioned in an intersection of two of the scribe lines; wherein the scribe lines have a first minimum dimension and the one or more alignment marks have a second minimum dimension that is greater than the first minimum dimension. Methods and additional apparatus are disclosed.

Abstract: An integrated circuit having PMOS, NMOS and NPN transistors is described for applications in which both digital and analog circuits are required. The integrated circuit is designed to allow standard CMOS cells to be used in the integrated circuit without redesign. A P+ substrate (48) is provided upon which a first P- epitaxy layer (46) is formed. N+ DUF regions (50,52) are provided for the PMOS and NPN transistors, respectively. The base region (68) is formed in an Nwell (58) by implantation and diffusion. Before diffusion, a nitride layer (70) is formed over the base (68) to provided an inert annealing thereof. The base diffusion and collector diffusion occurs before the CMOS channel stop and source/drain diffusions in order to prevent altering diffusion times for the MOS transistors.