Patents by Inventor Arnold Chow

Arnold Chow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6670829
    Abstract: A bus switch has a p-channel and an n-channel transistor in parallel between two buses. When power is disconnected to the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel transistor. This biasing keeps the p-channel transistor turned off. A gate connecting p-channel transistor connects the hot bus to the p-channel gate node, while a substrate connecting p-channel transistor connects the hot bus to the substrate under the p-channel transistor. A third connecting p-channel transistor connects the hot bus to a power-down node. The power-down node is normally driven low through a delay line when power is applied. The power-down node is applied to the gate of a source transistor that connects power to the substrate and to an inverter that normally drives the p-channel gate node.
    Type: Grant
    Filed: July 19, 2002
    Date of Patent: December 30, 2003
    Assignee: Pericom Semiconductor Corp.
    Inventor: Arnold Chow
  • Patent number: 6608517
    Abstract: A bus switch has an n-channel bus-switch transistor between two buses and a p-channel pullup transistor. When power is disconnected from the bus switch, and one bus is hot and has a voltage above ground, this higher voltage is conducted to the gate and substrate of the p-channel pullup transistor. This biasing keeps the p-channel transistor turned off. When power is off, a connecting p-channel transistor connects the higher voltage on the hot bus to the p-channel gate node, while an inverting p-channel transistor connects the gate node to the substrate under the p-channel transistor. Inverting transistors receive an inverse enable signal and drive the gate node when power is applied, turning on the pullup transistor when the n-channel bus-switch transistor is off, and vice-versa. The gate node is fed back and applied to the gate of a source transistor that connects power to the substrate.
    Type: Grant
    Filed: August 30, 2002
    Date of Patent: August 19, 2003
    Assignee: Pericom Semiconductor Corp.
    Inventors: Arnold Chow, Kwong Shing Lin
  • Patent number: 6359478
    Abstract: A large pull-down voltage-output-low VOL transistor is placed in parallel with a smaller pull-down switching transistor. The smaller switching pull-down transistor is turned on during switching. Once switching has nearly completed, the larger pull-down VOL transistor is turned on to provide a current sink for maintaining a VOL close to ground. Switching current is limited by the smaller switching pull-down transistor, while a large static sink current is provided by the VOL transistor to meet VOL requirements. The gate of the VOL transistor is controlled by p-channel and n-channel data transistors that are controlled by the data input, and p-channel and n-channel feedback transistors with gates connected to the buffer output. An upper n-channel transistor provides current to an intermediate node at the drain of the p-channel feedback transistor, keeping it near an intermediate voltage.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: March 19, 2002
    Assignee: Pericom Semiconductor Corp.
    Inventor: Arnold Chow
  • Patent number: 6075400
    Abstract: A bus switch has control of the timing of turning on and off the main p-channel and n-channel transistors that connect two network nodes. A pair of cross-coupled NAND gates form a set-reset S-R latch that controls the gates of the main p-channel and n-channel transistors. The S-R latch controls the timing so that the main p-channel and n-channel transistors switch at about the same time, canceling much of each other's injected charge. Since the main p-channel is larger due to the lower hole mobility, an excess of injected charge from the p-channel transistor remains. This excess charge is cancelled by opposite charge injected by compensating transistors. The compensating transistors are also p-channel devices, but are driven with a logical inverse of the gate of the main p-channel transistor. This produces a charge with opposite polarity to the excess charge from the main p-channel transistor.
    Type: Grant
    Filed: August 13, 1998
    Date of Patent: June 13, 2000
    Assignee: Pericom Semiconductor Corp.
    Inventors: Ke Wu, Arnold Chow