Abstract: A mechanism is provided to address a structure under test and to identify a point of failure. A test open line carries a signal that indicates whether a structure under test is open or closed. A test short line carries a signal that indicates whether a structure under test is shorted. A test structure may include an array of cells, where each cell includes a circuit including structures to test. The cells may be scanned using scan only latches and signals on the test open and/or test short lines may be recorded. A test circuit may include a digital mode and an analog mode. The digital mode provides an open or closed value. The analog mode includes a programmable load. The output of the analog mode provides a resistance value that is relative to the programmable load.

Abstract: A circuit for testing a differential current switching logic circuit of the type including: a bias potential, two resistors connected to the bias potential, and apparatus responsive to an input signal for sinking a first current through a selected one of the resistors so as to generate first and second differential output signals at the resistors. The circuit includes first, second, and third transistors, each having first and second terminals for conducting a current responsive to a signal applied to a control terminal. Apparatus are provided for supplying a current. The first transistor has its first terminal connected to the current supplying means, and its second terminal connected to a circuit node. The second transistor has its first terminal connected to the circuit node, its second terminal connected to the bias potential, and its control terminal connected to sense the potential at a selected one of the resistors.