Abstract: Various arrangements for using a positioning tag to facilitate control of a smart home device are presented herein. A communication sessions can be established between a control device and a positioning tag via a first device-to-device communication protocol. In response to a trigger event indicative of a user desiring to control the separate smart home device being detected, a positioning enablement message can be transmitted to the positioning tag via the first device-to-device communication protocol. A signal used for positioning is transmitted by the positioning tag using a second device-to-device communication protocol. Based on the received signal via the second device-to-device communication protocol, an interface that controls the smart home device is activated.

Abstract: Example embodiments relate to devices for gesture detection that incorporate ultra-wideband (UWB) transceivers. An example device includes a first UWB transceiver configured to transmit and receive UWB signals to communicate with a second UWB transceiver. The UWB signals are indicative of an orientation and a position of the first UWB transceiver relative to the second UWB transceiver. The second UWB transceiver corresponds to a first controlled device. The device also includes a memory and a processor. The processor is configured to identify one or more gestures traced out by the device based on the UWB signals. The processor is also configured to cause the first UWB transceiver to transmit a command UWB signal to the second UWB transceiver based on the one or more identified gestures. The command UWB signal provides an instruction to the first controlled device.

Abstract: Devices are provided that include radar circuits arranged to send and receive radar signals that can be used to, for example, detect gestures performed in the vicinity of the device. Arrangements of the circuits and associated antennas allow for the device to have no bezel or a minimal bezel.

Abstract: A phased-array antenna includes an antenna layer of a stacked printed circuit board, a ground plane layer of the stacked printed circuit board spaced apart from the antenna layer, and a first dielectric layer of the stacked printed circuit board disposed between and in opposed contact with the antenna layer and the ground plane layer. The antenna layer includes an associated metal patch pattern defined by a series of slots. The stacked printed circuit board defines a thickness extending between a top end of the stacked printed circuit board and a bottom end of the stacked printed circuit board. The phased-array antenna includes a series of ground vias extending between the top and bottom ends of the stacked printed circuit board. The ground vias are configured to suppress surface waves propagating across the stacked printed circuit board.

Abstract: A method including identifying clusters of antenna elements of a phased array antenna. For each cluster of antenna elements, the method includes identifying a reference antenna element of the cluster of antenna elements and identifying pairs of calibration antenna elements of the cluster of antenna elements. For each pair of calibration antenna elements, the method includes executing a calibration routine configured to determine a calibration adjustment for each antenna element of the pair of calibration antenna elements based on the reference antenna element. The method also includes determining a leveling adjustment for each antenna element of the phased array antenna. The method further includes adjusting the element gain and the element phase of each antenna element of the phased array antenna based on the corresponding leveling adjustment to equalize a transmission gain and a transmission phase of each signal path of the phased array antenna.

Abstract: A phased-array antenna includes an antenna layer of a stacked printed circuit board, a ground plane layer of the stacked printed circuit board spaced apart from the antenna layer, and a first dielectric layer of the stacked printed circuit board disposed between and in opposed contact with the antenna layer and the ground plane layer. The antenna layer includes an associated metal patch pattern defined by a series of slots. The stacked printed circuit board defines a thickness extending between a top end of the stacked printed circuit board and a bottom end of the stacked printed circuit board. The phased-array antenna includes a series of ground vias extending between the top and bottom ends of the stacked printed circuit board. The ground vias are configured to suppress surface waves propagating across the stacked printed circuit board.

Abstract: A circuit includes a power amplifier that includes a transformer having a primary winding and a secondary winding. The secondary winding has a first terminal and a second terminal. The circuit also includes a transmit/receive switch electrically connected between the first terminal of the secondary winding and electrical ground. The second terminal of the secondary winding is electrically connected to an antenna that transmits signals based on an output of the power amplifier and to an input of a second amplifier that is also connected to the antenna. The transmit/receive switch selectively switches between a closed position that connects the secondary winding to ground in a transmit mode and an open position that disconnects the secondary winding from ground in a receive mode.

Abstract: A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal.

Abstract: A method including identifying clusters of antenna elements of a phased array antenna. For each cluster of antenna elements, the method includes identifying a reference antenna element of the cluster of antenna elements and identifying pairs of calibration antenna elements of the cluster of antenna elements. For each pair of calibration antenna elements, the method includes executing a calibration routine configured to determine a calibration adjustment for each antenna element of the pair of calibration antenna elements based on the reference antenna element. The method also includes determining a leveling adjustment for each antenna element of the phased array antenna. The method further includes adjusting the element gain and the element phase of each antenna element of the phased array antenna based on the corresponding leveling adjustment to equalize a transmission gain and a transmission phase of each signal path of the phased array antenna.

Abstract: A method for operating a phase shifter chip RF self-test. The method includes outputting, by control hardware, a first signal from a phased locked loop to a pre-amplifier and an input peak detector, outputting, by the control hardware, a second signal from the pre-amplifier to a device under test, selecting, by the control hardware, a target level, and adjusting, by the control hardware, a pre-amplifier gain of the pre-amplifier to cause the input peak detector value to approximately match the target level. The input peak detector is configured to output an input peak detector value based on the first signal.

Abstract: Systems and techniques are disclosed for configuring a circuit containing a two-stage amplifier including a first stage containing at least a differential amplifier, a second stage containing at least a transistor, and a sensing circuit configured to provide a gate voltage to a compensation component. The compensation component may be configured to connect the first stage and the second stage and to generate a lead-lag compensation. The compensation component may contain a compensation capacitor and a variable compensation resistive component in series connection with the compensation capacitor.

Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Abstract: Systems and techniques are disclosed for configuring a circuit containing a two-stage amplifier including a first stage containing at least a differential amplifier, a second stage containing at least a transistor, and a sensing circuit configured to provide a gate voltage to a compensation component. The compensation component may be configured to connect the first stage and the second stage and to generate a lead-lag compensation. The compensation component may contain a compensation capacitor and a variable compensation resistive component in series connection with the compensation capacitor.

Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.

Abstract: A R2R ladder circuit implementation of a digital-to-analog convertor (DAC) may be configured to compensate for mismatch in each of a plurality of current sources in the R2R ladder circuit. The compensating of mismatch in each of the plurality of current sources may be achieved by adding one or more auxiliary current sources associated with each of the plurality of current sources, which may be used to provide pre-configured auxiliary current that would enable compensating for mismatch in current of an associated one of the plurality of current sources. For example, each of the plurality of current sources may have two auxiliary current sources, connected in parallel therewith, with one of two auxiliary current sources being switched to the positive-side and the other auxiliary current source being switched to the negative-side. The switching structure of the modified R2R ladder circuit may be implemented in any semiconductor technology (e.g., BiCMOS technology).