Patents by Inventor Arnold J D'Souza

Arnold J D'Souza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10389250
    Abstract: A DC-DC converter includes an inductor, and generates a regulated voltage from a power source. The current flow through the inductor is increased at a first rate in a first interval. In a second interval, the current flow through the inductor is either increased at a second rate or decreased at a third rate depending on whether the regulated voltage is required to be respectively less than or greater than a voltage of the power source. The current flow through the inductor is decreased at a fourth rate in a third interval. The sequence formed by the first interval, the second interval and the third interval is repeated, and followed for all values of the regulated voltage from a lower threshold to higher threshold. The higher threshold has a value greater than the voltage of the power source. The lower threshold is zero volts.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 20, 2019
    Assignee: Aura Semiconductor Pvt. Ltd
    Inventors: Hariharan Srinivasan, Arnold J D'Souza, Shyam Somayajula
  • Patent number: 10312868
    Abstract: A fully differential amplifier includes a first feedback resistance, a second feedback resistance, a first input resistance and a second input resistance. A first ratio of the first feedback resistance to the first input resistance is equalized with that of a reference ratio of a pair of reference resistances. Similarly a second ratio of the second feedback resistance to the second input resistance is also equalized with that of the reference ratio. Such equalization operations may be performed during a calibration phase prior to normal operation of the fully differential amplifier. Accordingly, when a common mode voltage present on each of the first output terminal and the second output terminal varies during normal operation, contribution of an erroneous differential signal component across the pair of differential output terminals is prevented.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: June 4, 2019
    Assignee: AURA SEMICONDUCTOR PVT. LTD
    Inventors: Arnold J D'Souza, Shyam Somayajula
  • Patent number: 10312872
    Abstract: Shoot-through condition in a component containing an amplifier with a push-pull output stage is managed. A first current in a first transistor of the output stage is mirrored to generate a first mirrored current. A second current in a second transistor of the output stage is mirrored to generate a second mirrored current. A sum of the first mirrored current and said second mirrored current is generated. When a magnitude of the sum exceeds a first pre-determined threshold, a respective control voltage of the first transistor and the second transistor is adjusted to reduce the first current and the second current at least until the sum falls below a second pre-determined threshold. In an embodiment, the first pre-determined threshold equals the second pre-determined threshold. In an embodiment, the component is a class-L power amplifier.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: June 4, 2019
    Assignee: Aura Semiconductor Pvt. Ltd
    Inventors: Arnold J D'Souza, Shyam Somayajula
  • Publication number: 20180316322
    Abstract: Shoot-through condition in a component containing an amplifier with a push-pull output stage is managed. A first current in a first transistor of the output stage is mirrored to generate a first mirrored current. A second current in a second transistor of the output stage is mirrored to generate a second mirrored current. A sum of the first mirrored current and said second mirrored current is generated. When a magnitude of the sum exceeds a first pre-determined threshold, a respective control voltage of the first transistor and the second transistor is adjusted to reduce the first current and the second current at least until the sum falls below a second pre-determined threshold. In an embodiment, the first pre-determined threshold equals the second pre-determined threshold. In an embodiment, the component is a class-L power amplifier.
    Type: Application
    Filed: April 27, 2018
    Publication date: November 1, 2018
    Applicant: Aura Semiconductor Pvt. Ltd
    Inventors: Arnold J. D'Souza, Shyam Somayajula
  • Publication number: 20180309413
    Abstract: A fully differential amplifier includes a first feedback resistance, a second feedback resistance, a first input resistance and a second input resistance. A first ratio of the first feedback resistance to the first input resistance is equalized with that of a reference ratio of a pair of reference resistances. Similarly a second ratio of the second feedback resistance to the second input resistance is also equalized with that of the reference ratio. Such equalization operations may be performed during a calibration phase prior to normal operation of the fully differential amplifier. Accordingly, when a common mode voltage present on each of the first output terminal and the second output terminal varies during normal operation, contribution of an erroneous differential signal component across the pair of differential output terminals is prevented.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 25, 2018
    Inventors: Arnold J. D'Souza, Shyam Somayajula
  • Patent number: 9319495
    Abstract: A power amplifier containing a DC-DC converter, a linear amplifier and a control block. The DC-DC converter receives power from a power source and generates a regulated power supply voltage whose magnitude is controlled by the magnitude of a control signal provided to the DC-DC converter. The linear amplifier receives an input signal and generates a power-amplified output signal, and receives the regulated power supply voltage for operation. The control block is coupled to receive the input signal, and generates the control signal with a magnitude based on the amplitude of the input signal. The regulated power supply voltage is modulated based on the amplitude of the input signal, for peak-to-peak amplitudes of the power-amplified output greater than or less than or equal to the magnitude of the power source. High efficiency for the power amplifier is thereby obtained.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: April 19, 2016
    Assignee: AURA SEMICONDUCTOR PVT. LTD
    Inventors: Arnold J D'Souza, Hariharan Srinivasan, Shyam Somayajula
  • Publication number: 20150045095
    Abstract: A power amplifier containing a DC-DC converter, a linear amplifier and a control block. The DC-DC converter receives power from a power source and generates a regulated power supply voltage whose magnitude is controlled by the magnitude of a control signal provided to the DC-DC converter. The linear amplifier receives an input signal and generates a power-amplified output signal, and receives the regulated power supply voltage for operation. The control block is coupled to receive the input signal, and generates the control signal with a magnitude based on the amplitude of the input signal. The regulated power supply voltage is modulated based on the amplitude of the input signal, for peak-to-peak amplitudes of the power-amplified output greater than or less than or equal to the magnitude of the power source. High efficiency for the power amplifier is thereby obtained.
    Type: Application
    Filed: August 1, 2014
    Publication date: February 12, 2015
    Inventors: Arnold J D'Souza, Hariharan Srinivasan, Shyam Somayajula