Abstract: A technique for implementing a programmable thermal model of an integrated circuit component such as a central processing unit (CPU) and its associated heat sink. The model estimates the die temperature of the component as if there were no cooling devices present in the system such as a forced air cooling fan by integrating the thermal energy added when the component is active and by integrating the thermal energy removed when it is idle. A programmable power value may be used to represent the heat added to the model at each model sample period. The effect of a heat sink in cooling the idle component may be modeled by reducing the value of the heat accumulator by a predetermined fractional amount during each sample period. The decay time constant for the model may be changed by then adjusting the sample period.

Abstract: The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.

Abstract: An apparatus for determining a plurality of video signal characteristics including analog video frequency, horizontal sync frequency and vertical sync frequency produced by a graphics controller providing the video signal to a video display monitor, includes a memory storing bits which correspond to a set of operating characteristics of the video display monitor, a first circuit coupled to the memory for producing voltage fluctuations on a line based on the stored bits in response to a signal which corresponds to a command to set the characteristics of the video signal provided to the video display monitor, and a second circuit for sensing the voltage fluctuations so as to permit determination of the set of operating characteristics. The first circuit includes a switch operatively coupled between a video line and ground to allow grounding of the video line based on the bits so as to produce the voltage fluctuations. The second circuit comprises a logic element for detecting the voltage fluctuations.

Abstract: A system architecture of a personal computer is modified to increase overall performance including the display of video signals while maintaining PC compatibility. A video control circuit is positioned onto a motherboard so that it directly interfaces with a local bus of a processing unit. The processing unit may include, for example, a 80386 microprocessor and a 82396 cache controller or simply a 80386 or 80486 microprocessor. As a result, the processing unit can directly read data from and write data to the video controller without always having to traverse the peripheral bus. Video data is thus transferred at the rate at which the processing unit operates and not at the slower rate of the peripheral bus.