Abstract: Embodiments include herein are directed towards a method for electronic circuit design. Embodiments may include receiving a selection of an instance associated with an electronic design at an electronic design schematic displayed on a graphical user interface. Embodiments may also include selecting a corresponding instance within an electronic design layout displayed on a graphical user interface. Embodiments may further include receiving a selection of a source topology and routing at the electronic design layout displayed on the graphical user interface, based upon at least in part, the source topology.

Abstract: Embodiments include herein are directed towards a method for electronic circuit design is provided. Embodiments may include allowing, at a graphical user interface, a user to initiate a co-design mode associated with an electronic design. Embodiments may further include allowing, at the GUI, the user to select a shape to trace connectivity from. Embodiments may also include tracing the connectivity of the shape across one or more overlaps and identifying one or more pins associated with the connectivity. Embodiments may further include determining a correct pin from an instance associated with the connectivity and displaying the connectivity at the GUI.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with real-time modeling. An electronic design may be prepared for an analysis that programmatically sweeps across multiple values of a new parameter for multiple instances in the electronic design. The analysis may be performed on the electronic design at least by adding the new parameter to the analysis engine and by sweeping the new parameter across the multiple values to generate an analysis result. The electronic design may then be updated based at least in part upon the analysis result.

Abstract: An approach is described for a method, system, and product for detection of contours for data pads of a device having a free form contour, clustering integrated circuit pads and data pads, performing any angle routing based on a contour angle, and performing resistance balancing. For example, data pads of a display device having one or more curved contours (e.g. data pads arranged on an arc) are identified. Corresponding data pads and integrated circuit pads are then grouped together for routing interconnections and subsequently routed using any angle routing instead of merely routing interconnections with turns having 90-degree or 45-degree angles. Finally, the routed interconnects may be further refined/modified to balance resistances of the interconnections.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a schematic driven extracted view. These techniques identify a schematic of an electronic design, wherein the schematic exists in one or more design fabrics. These techniques further determine an extracted model for characterizing a behavior of the electronic design based at least in part upon the schematic, determine a hierarchical level in a design fabric of the one or more design fabrics of the schematic, and characterize the electronic design with at least an extracted view.

Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing electronic designs with electronic design simplification techniques. These techniques identify an input for simplifying an electronic design and generates a simplified electronic design at least by performing layout simplification on the electronic design. A characterization input may be determined for subsequent characterization of the simplified electronic design. An electromagnetic behavior of the simplified electronic design may then be characterized using at least the characterization input.

Abstract: Disclosed are methods, systems, and articles of manufacture for probing a multi-fabric electronic design that spans across multiple design fabrics. These techniques identify a single layout editor, a first electronic design in a first design fabric, and a second electronic design in a second design fabric. An input for probing a circuit component in the first electronic design may further be identified at a user interface of a computing system. The circuit component being probed is connected to an instance of the second electronic design. In response to the input, one or more co-design modules render a representation of the first layout with emphasized circuit components in the first design fabric and the second design fabric, wherein the one or more co-design modules are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system.

Abstract: Disclosed are methods, systems, and articles of manufacture for reducing interferences and disturbances in a multi-fabric electronic design. These techniques identify connectivity for an electronic design that includes design data in multiple design fabrics. One or more interference modules are executed to detect a loop in the electronic design with at least the connectivity. These techniques further execute the one or more interference reduction modules to determine at least one critical circuit component upon which the loop exerts a negative impact. One or more remedial actions are then triggered to reduce or eliminate the negative impact on the critical circuit component design.

Abstract: Disclosed are methods, systems, and articles of manufacture for determining layout equivalence between a plurality of versions of a single layout of a multi-fabric electronic design. These techniques identify a first version and a second version of a layout of an electronic design that spans across multiple design fabrics. One or more collaborative comparator modules are executed to determine whether the first version is identical to or different from the second version of the layout. These techniques further modify the first version or the second version of the layout with discrepancy annotation.

Abstract: Disclosed are methods, systems, and articles of manufacture for binding and annotating an electronic design with a schematic driven extracted view. These techniques identify a schematic design and an extracted view of an electronic design and bind the schematic design with the extracted view. The resulting binding information concerning binding the schematic design with the extracted view is stored in a data structure. The schematic design may be annotated with extracted view information pertaining to the extracted view based at least in part upon the binding information. A response to a user action may be automatically generated based in part or in whole upon the extracted view information or the binding information.

Abstract: The present disclosure relates to a computer-implemented method for electronic circuit design awareness. Embodiments may include providing, using a processor, an electronic design having a package layout and a die layout associated therewith. Embodiments may also include displaying at a graphical user interface, the package layout and allowing, at the graphical user interface, a user to edit the package layout. Embodiments may further include determining, using the processor, an impact of the edit on the die layout and in response to the edit, mirroring the edit at the die layout.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing schematic driven extracted views for an electronic design. These techniques identify a schematic circuit component design represented by a schematic symbol from a schematic design and identifying layout device information from a layout of the electronic design. An extracted view is generated anew or updated from an existing extracted view at least by placing and interconnecting a symbol in the schematic design based at least in part upon the layout device information. The electronic design may be further updated based in part or in whole upon results of performing one or more analyses on the extracted view.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing a schematic circuit design component as a transmission line model in a schematic driven extracted view for an electronic design. These techniques identify a schematic circuit component design form a schematic design of an electronic design and identify or determine layout device information of a layout circuit component design corresponding to the schematic circuit component design. An extracted view may be generated or identified for the electronic design at least by using a transmission line model based in part or in whole upon connectivity information or a hierarchical structure of the electronic design. The electronic design may then be modified or updated based in part or in whole upon results of performing one or more analyses on the extracted view with the transmission line model.

Abstract: The present disclosure relates to a computer-implemented method for use in an electronic circuit design. Embodiments may include receiving, using at least one processor, the electronic circuit design and displaying, via a graphical user interface, a first device associated with the electronic circuit design. Embodiments may further include displaying, via the graphical user interface, a second device associated with the electronic circuit design. Embodiments may also include displaying, via the graphical user interface, inter-device connectivity between the first device and the second device and displaying intra-device connectivity between at least one of the first device and the second device, wherein the inter-device connectivity and the intra-device connectivity are visibly distinct.

Abstract: Embodiments include herein are directed towards a method for use in an electronic design environment is provided. The method may include receiving, using a processor, a parent fabric corresponding to a top layout fabric associated with an electronic design and receiving a child fabric corresponding to a child layout fabric associated with the electronic design. The method may further include receiving an electromagnetic (“EM”) model that represents one or more cross-fabric geometries associated with the electronic design and generating a hierarchical schematic representing each layout fabric, wherein the EM model is inserted into a parent schematic. The method may also include managing one or more interface connections between the hierarchical schematic.

Abstract: A benchmark test system captures and records root, or input, behavior from a user input device as one or more time-displaced samples of input. The system also separately captures and records the canvas, or visual, behavior of a user interface in response to the captured input as a series of time-displaced image frames. The image frames are analyzed for visual prompts occurring responsive to the input, and parameters of the image frames are determined. A parametric difference between corresponding ones of the root events and canvas responses is thereby computed, in order to determine a degree of visual responsiveness for the user interface software respective to the root input.

Abstract: A version management system for fluid guard ring (FGR) PCells uses one or more new version management parameters that are added to the FGR PCell definition to manage the source code versions for a PCell. The system saves instance layout information with a version management parameter that identifies the current PCell source code version for each FGR PCell instance. When evaluated using a newer version of the PCell source code, the instance layout information generated with a previous version of PCell source code can be retrieved. The retrieved layout information will be used during evaluation of the PCell to ensure the integrity of the PCell geometries that were previously verified. The saved layout information will be uniquely identifiable with a hash code of the name-value pairs for one or more parameters associated with the PCell instance.

Abstract: A system, method, and computer program product for automatically placing contact cuts in integrated circuit layouts, particularly in guard rings, inter-layer via connections, and various space-filling structures typically defined by polygons or paths. Areas to be filled with contact cuts are partitioned horizontally and vertically, and decomposed into shared and exclusive type regions that are sorted directionally. Contact cuts are placed in each region according to its type and according to relevant design rules on contact cut spacing and enclosure constraints. Contact cuts that may cause design rule violations are deleted. Narrow jogs or cuts, merged shared regions, and non-orthogonal edges or segments in the decomposed regions are handled by alternate embodiments. The result is automated contact cut placement, even for merged/chopped layout features, that is generally more symmetric, collinear, and adds an optimal number of contact cuts in most cases than with existing tools.