Abstract: An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between selected edges of the same or different ones of the DUT output signal, the DUT input signal, and a reference clock signal. Additionally, when the DUT input and output signals convey repetitive patterns, the IC can measure the voltage of the DUT input out output signal as selected points within the pattern by comparing it to an adjustable reference voltage. Processing circuits external to the IC program the IC to provide a specified amount of jitter to the test signal, control the measurements carried out by the measurement circuit, and process measurement data to determine the amount of jitter and other characteristics of the DUT output signal, and to calibrate the jitter in the DUT input signal.

Abstract: An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator for generating a series of trigger signal edges in response to selected DUT output signal edges occurring during separate repetitions of the digital signal pattern. The trigger generator can be configured to generate each trigger signal edge in response to the same or a different edge of the digital signal pattern. The apparatus determines when a DUT output signal edge occurs by determining when the DUT output signal rises above or falls below adjustable reference voltages. The apparatus alternatively responds to each trigger signal edge by measuring a period between two different edges of the digital signal pattern and or by repetitively sampling the DUT output signal to determine its state.

Abstract: A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value identifying a position within the pattern of a last occurring edge of the digital signal and generates second data having a value identifying a position of a particular edge within the pattern that is to initiate a next assertion of the trigger signal. The triggering circuit asserts the trigger signal when the first and second data values match and de-asserts the trigger signal when the first and second data do not match. In a repetitive mode of operation, the triggering circuit keeps the second data value constant so that it always asserts the trigger signal in response to the same edge of the pattern.

Abstract: A skew correction system incorporated into a transmitter forwarding a differential signal on a differential lane monitors returning signal reflections when the receiving end of the differential lane is appropriately terminated. Based on an analysis of the reflections, the skew correction system adjusts the relative timing of complementary edges of the differential signal departing the transmitter so as to substantially eliminate skew at the receiving end of the differential lane.

Abstract: A self-calibrating strobe signal generator for a BIST circuit responds to an edge of an input strobe signal by generating corresponding edges of first and second strobe signals separated in time by a target delay specified by input data. The strobe signal generator includes a multiplexer, a delay circuit and a controller. The multiplexer normally provides the input strobe signal as a multiplexer output signal to the delay circuit which generates edges in each of the first and second strobe signals in response to each edge in the multiplexer output signal with a programmable delay between corresponding first and second strobe signal edges.

Abstract: A jitter generator produces a jittery test signal for use in performing a jitter test on an integrated circuit (IC) device under test (DUT). The jitter generator includes a programmable delay circuit for delaying a non-jittery input signal with a varying delay controlled by input digital delay control data to produce the test signal. A pattern generator supplies a sequence of delay control data to the programmable delay circuit causing it to produce a desired jitter pattern in the test signal. During a calibration process, a measurement unit feeds the test signal back to the input of the programmable delay circuit, causing the test signal to oscillate with a period proportional to the delay through the delay circuit. The measurement unit then measures the period of the test signal for various values of delay control data and reports measurement results.

Abstract: A jitter measurement system measures timing variations or “jitter” in a periodic signal waveform as provided, for example, by a phase-locked loop (PLL). In one implementation, the jitter measurement system includes a period gate generator that generates a gate signal with the instantaneous period of output signal waveform FVCO generated by the PLL. The gate signal includes a leading edge and a trailing edge and is delivered to a pair of triggered oscillators that provide respective oscillator output signals with substantially matched frequencies. The oscillators are triggered at the respective leading and trailing edges of the gate signal. The oscillator output signals are delivered to respective oscillation counters and to a coincidence detector. The oscillation counters count the periods of the respective oscillator output signals from when they are triggered until the coincidence detector detects coincidence between the signals (e.g., coincidence between the trailing edges of the signals).

Abstract: A jitter measurement system measures timing variations or “jitter” in a periodic signal waveform as provided, for example, by a phase-locked loop (PLL). In one implementation, the jitter measurement system includes a period gate generator that generates a gate signal with the instantaneous period of output signal waveform FVCO generated by the PLL. The gate signal includes a leading edge and a trailing edge and is delivered to a pair of triggered oscillators that provide respective oscillator output signals with substantially matched frequencies. The oscillators are triggered at the respective leading and trailing edges of the gate signal. The oscillator output signals are delivered to respective oscillation counters and to a coincidence detector. The oscillation counters count the periods of the respective oscillator output signals from when they are triggered until the coincidence detector detects coincidence between the signals (e.g., coincidence between the trailing edges of the signals).

Abstract: A programmable delay circuit employs a relatively slow conventional silicon emitter-coupled transistor pair and a relatively fast silicon/germanium heterojunction emitter-coupled transistor pair. The bases of both transistor pairs are driven by an input signal to be delayed. The collectors of transistors of both pairs are linked to a voltage source through a pair of load resistors, with an output signal appearing across the collectors of both transistor pairs. A current source draws complementary adjustable load currents through the two transistor pairs. Although the sum of the two load currents is a constant, the relative amount of load current drawn though the two transistor pairs is adjustable.

Abstract: A CMOS buffer amplifier can accept input signals and produce output signals that are within one half of the enhancement threshold voltage of the power supply voltages. These characteristics make this buffer amplifier ideal for use with low voltage CMOS circuitry with sub-micron geometries. The buffer amplifier contains two differential amplifiers, the output of both being combined and coupled to an output node. Each differential amplifier has matched input transducing devices on each of its inputs. One of these couples the input of the buffer amplifier to one of the inputs of the differential amplifier, while the other one couples the output of the buffer amplifier as feedback to the other side of the same differential amplifier. The pair of input transducing devices providing input to one differential amplifier are matched and suitable for operation in a higher voltage range than are the matched pair providing input to the other differential amplifier.

Abstract: A multi-chip module development substrate (12) contains embedded test circuitry (30). Vias (38) connect I/O channels (Cn) of the test circuitry with conductive runs in interconnect layers (16,18) that are part of an interconnect structure (17) of the development substrate. Integrated circuit chips (14) are then mounted on the multi-chip module development substrate in selected electrical contact with the conductive runs. The embedded test circuitry includes multiple timing analyzer circuits (TAn) and multiple analog probe circuits en). In a preferred embodiment, these timing analyzer circuits and analog probe circuits are provided in redundant pairs, with a pair of each associated with each of the I/O channels. Multiple pairs of each kind of circuit are grouped within test cells (70) physically arranged in rectangular areas. Adjacent test circuit cells may be rotated with respect to each other to achieve more efficient connections to interconnect structure.

Abstract: A method for evaluating an electrical signal is disclosed. This method is especially useful for evaluating analog signals within an integrated circuit or other inaccessible location. A reference histogram is derived from either a simulation of a desired waveform or from sampling a desired waveform signal. This reference histogram is subtracted from a test results histogram to produce a variance histogram. The variance histogram can be further evaluated to determine characteristics of the electrical signal under test and/or to produce a figure of merit for the circuitry producing the signal under evaluation. Before the difference between the test results histogram and the reference histogram is taken, normalization, offset calculation, gain adjustment, and noise floor adjustment may be performed on the test results histogram, and these values may be exported to further aid in characterization of the signal under evaluation.

Abstract: An adjustable precision delay circuit includes a series of inverter gates and a multiplexer for selecting any of their outputs or the input to the series. The polarity of the signal input to this circuit is controlled so that any selected output always has the same predetermined polarity, thereby eliminating timing errors arising from factors that vary with the polarity of the output.

Abstract: A variable reference voltage generator provides variable voltage rails for a delay element in order to control the amount of delay of an electrical signal through the delay element. A control signal, such as an error signal from a phase locked loop, is input to a pair of operational amplifiers, one configured as a unity gain buffer and the other configured as a positive gain feedback amplifier. The one amplifier is coupled to one input of a modified Magee inverter circuit and the other amplifier is coupled to the other input of the modified Magee inverter circuit. The variable voltage rails are taken from the output buffers of the modified Magee inverter circuit. To provide a range of voltages for the variable voltage rails that approaches the power supply voltages, the two outer transistors of the modified Magee inverter circuit are converted to voltage sources so that the control signal is added to the positive power supply voltage and subtracted from the negative power supply voltage.

Abstract: A timing analyzer for embedded testing of printed circuit boards, integrated circuits or multi-chip modules is in the form of an integrated circuit that may be included as part of the printed circuit board, integrated circuit or multi-chip module being tested. Each channel of a data path to be tested has a timing analyzer circuit that may be coupled into the path when enabled for testing. The timing analyzer circuit has instruction memories that are loaded with time event commands via a suitable program bus, such as a boundary scan interface. Each event command has a clock portion, an interpolation portion and a drive output portion. A counter counts down the clock portion using a system clock from the board/circuit/module to produce a terminate pulse. The terminate pulse is delayed by an increment less than one period of the system clock by a delay interpolator, the amount of delay being determined by the interpolation portion, to generate a trigger signal.

Abstract: A programmable analog multi-channel probe system is embedded within a device under test for coupling test points to external measurement points of the device under test. Programmable input buffer amplifiers are coupled to the test points to couple the data at those points to their outputs when enabled. The data from the input buffer amplifiers are input to respective routers to provide a plurality of outputs. Each common output from the routers is coupled as an input to an output buffer amplifier that provides the data as an output when enabled. The data at the output of the output buffer amplifiers is converted to a differential signal for transmission to the external measurement point by differential input/output amplifiers that have a reference level, selected from a plurality of reference levels including an internal reference level, as an input for comparison with the data from the output buffer amplifiers.

Abstract: In a pipelined direct digital synthesis system (FIG. 3), new increment data (124) and/or phase modulation data (122) are input delay equalized by providing the data to a series of switch blocks (132), each switch block corresponding to a stage of the accumulator (124). Each switch block includes a multiplexer (132) for selecting among the new increment data, phase modulation data, and previously stored increment data, and includes a flip-flop circuit (134) for storing the selected increment data. A shift register (140) provides select signals (146) to each of the multiplexers. In operation, as a single bit propagates through the shift register, the select signals sequentially control the multiplexers to sequentially interleave blocks of selected increment data into respective accumulator stages in ascending order of binary significance. The invention thereby substantially reduces the input delay equalization circuitry necessary for coherent operation.

Abstract: A low distortion optic fiber network having a feedback system which injects pilot tones into a base band input signal directly modulating an LED, optically detects the output resulting from the pilot tones, digitally samples the detected signal, and generates correction coefficients. The correction coefficients and the base band input signal are input to a correction circuit that pre-distorts the input signal in a non-linear manner and uses the distorted signal to modulate the LED. Pre-distorting the LED input signal compensates for the non-linearities of diode transfer characteristics and intermodulation between signals in the network thereby reducing harmonic and intermodulation distortion.

Abstract: A low distortion light source comprising a light emitting diode and a compensating diode connected in parallel with respect to a D.C. bias current and in anti-series with respect to an A.C. signal source. The compensating diode is selected to have a forward resistance similar to the forward resistance of the LED. Adjusting the D.C. bias current through the diodes to be approximately equal matches the forward resistance characteristics and substantially reduces the undesired intermodulation products.

Abstract: A bipolar-CMOS (Bi-CMOS) digital interface circuit (50) of the present invention provides an interface between a bipolar digital circuit (52) and a CMOS digital circuit (54). The digital interface circuit includes a digital transform circuit (56) that receives a bipolar logic signal generated by the bipolar digital circuit and transforms the signal into an intermediate logic signal whose voltage waveform is positioned symmetrically about a logic threshold generated by a CMOS digital input circuit (58). The CMOS digital input circuit receives the intermediate logic signal and generates a CMOS logic signal that is delivered to the CMOS digital circuit, thereby to interface the CMOS digital circuit with the bipolar digital circuit.