Patents by Inventor Arnold N. Sodder

Arnold N. Sodder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7328277
    Abstract: Significant performance improvements can be realized in data processing systems by confining the operation of a processor within its internal register file so as to reduce the instruction count executed by the processor. Data, which is sufficiently small enough to fit within the internal register file, can be transferred into the internal register file, and execution results can be removed therefrom, using direct memory accesses that are independent of the processor, thus enabling the processor to avoid execution of load and store instructions to manipulate externally stored data. Further, the data and execution results of the processing activity are also accessed and manipulated by the processor entirely within the internal register file. The reduction in instruction count, coupled with the standardization of multiple processors and their instruction sets, enables the realization of a highly scaleable, high-performing symmetrical multi-processing system at manageable complexity and cost levels.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: February 5, 2008
    Assignee: Enterasys Networks, Inc.
    Inventors: Terrence Hussey, Donald W. Monroe, Arnold N. Sodder
  • Publication number: 20010049744
    Abstract: Significant performance improvements can be realized in data processing systems by confining the operation of a processor within its internal register file so as to reduce the instruction count executed by the processor. Data, which is sufficiently small enough to fit within the internal register file, can be transferred into the internal register file, and execution results can be removed therefrom, using direct memory accesses that are independent of the processor, thus enabling the processor to avoid execution of load and store instructions to manipulate externally stored data. Further, the data and execution results of the processing activity are also accessed and manipulated by the processor entirely within the internal register file. The reduction in instruction count, coupled with the standardization of multiple processors and their instruction sets, enables the realization of a highly scaleable, high-performing symmetrical multi-processing system at manageable complexity and cost levels.
    Type: Application
    Filed: March 2, 2001
    Publication date: December 6, 2001
    Inventors: Terrence Hussey, Donald W. Monroe, Arnold N. Sodder
  • Patent number: 5949784
    Abstract: A technique for designating output interfaces through which a data unit is transmitted in point-to-multipoint transmission is disclosed. An indicating word having a flag field, a group indicator field and a bitmask field is employed. The number of bits in the bitmask is less than the total number of output interfaces. The bitmask field has a plurality of bits for indicating output interfaces and the group indicator field designates an offset value such that the bitmask field and group indicator field together indicate particular individual output interfaces. The flag field serves as notification that additional such words are to be received in association with a given point-to-multipoint data unit transmission.
    Type: Grant
    Filed: May 1, 1997
    Date of Patent: September 7, 1999
    Assignee: 3Com Corporation
    Inventor: Arnold N. Sodder