Abstract: This document describes techniques and systems that enable battery state estimation. The techniques and systems may be used to determine a shut-down voltage for a battery of an electronic device. Additionally or alternatively, the techniques and systems may be used to determine a state-of-charge of the battery, which may be determined relative to the shut-down voltage. The techniques and systems use current or expected conditions at the battery to estimate the battery state. These techniques can allow the electronic device to dynamically set a shut-down voltage, rather than using a fixed shut-down voltage over the life of the electronic device. The dynamically set shut-down voltage can provide a low margin, and therefore a greater portion of battery capacity, when operating in good conditions and provide a relatively large margin that is sufficient for poor conditions.

Abstract: This document describes techniques and systems that enable battery state estimation. The techniques and systems may be used to determine a shut-down voltage for a battery of an electronic device. Additionally or alternatively, the techniques and systems may be used to determine a state-of-charge of the battery, which may be determined relative to the shut-down voltage. The techniques and systems use current or expected conditions at the battery to estimate the battery state. These techniques can allow the electronic device to dynamically set a shut-down voltage, rather than using a fixed shut-down voltage over the life of the electronic device. The dynamically set shut-down voltage can provide a low margin, and therefore a greater portion of battery capacity, when operating in good conditions and provide a relatively large margin that is sufficient for poor conditions.

Abstract: This document describes techniques and systems that enable battery state estimation. The techniques and systems may be used to determine a shut-down voltage for a battery of an electronic device. Additionally or alternatively, the techniques and systems may be used to determine a state-of-charge of the battery, which may be determined relative to the shut-down voltage. The techniques and systems use current or expected conditions at the battery to estimate the battery state. These techniques can allow the electronic device to dynamically set a shut-down voltage, rather than using a fixed shut-down voltage over the life of the electronic device. The dynamically set shut-down voltage can provide a low margin, and therefore a greater portion of battery capacity, when operating in good conditions and provide a relatively large margin that is sufficient for poor conditions.

Abstract: This document describes techniques and systems that enable battery state estimation. The techniques and systems may be used to determine a shut-down voltage for a battery of an electronic device. Additionally or alternatively, the techniques and systems may be used to determine a state-of-charge of the battery, which may be determined relative to the shut-down voltage. The techniques and systems use current or expected conditions at the battery to estimate the battery state. These techniques can allow the electronic device to dynamically set a shut-down voltage, rather than using a fixed shut-down voltage over the life of the electronic device. The dynamically set shut-down voltage can provide a low margin, and therefore a greater portion of battery capacity, when operating in good conditions and provide a relatively large margin that is sufficient for poor conditions.

Abstract: A phased array antenna system includes an array of antennas having first antenna and second antennas disposed equidistantly from a third antenna. The first antenna is associated with a first gain and a first phase and the second antenna is associated with a second gain and a second phase. The first antenna receives a first reference signal corresponding to a calibration reference signal transmitted by the third antenna, and the second antenna receives a second reference signal corresponding to the calibration reference signal transmitted by the third antenna. The second receiver module is configured to adjust the second gain and the second phase associated with the second antenna to match the first gain and the first phase associated with the first antenna by comparing the first reference signal received by the first antenna with the second reference signal received by the second antenna.

Abstract: A phased-array antenna assembly includes an antenna board stack, a radome configured to cover the antenna board stack, and a casing configured to support the antenna board stack. The antenna board stack includes a central core, a bottom antenna unit defining a bottom thickness between a bottom surface of the central core and a bottom end of the antenna board stack, and a top antenna unit defining a top thickness between a top surface of the central core and the top end of the antenna board stack that is substantially equal to the bottom thickness. The bottom antenna unit includes two spaced apart bottom metal layers each associated with a different distance from the axis of symmetry. The top antenna unit includes two spaced apart top metal layers each associated with a corresponding one of the distances from the axis of symmetry associated with the bottom metal layers.

Abstract: A phased-array antenna assembly includes an antenna board stack, a radome configured to cover the antenna board stack, and a casing configured to support the antenna board stack. The antenna board stack includes a central core, a bottom antenna unit defining a bottom thickness between a bottom surface of the central core and a bottom end of the antenna board stack, and a top antenna unit defining a top thickness between a top surface of the central core and the top end of the antenna board stack that is substantially equal to the bottom thickness. The bottom antenna unit includes two spaced apart bottom metal layers each associated with a different distance from the axis of symmetry. The top antenna unit includes two spaced apart top metal layers each associated with a corresponding one of the distances from the axis of symmetry associated with the bottom metal layers.

Abstract: A method for active interference avoidance in unlicensed bands. The method includes receiving an electromagnetic signal having a transmission frequency, a transmission period, and an antenna pattern from a phased array antenna. The method also includes switching the transmission frequency from a first transmission frequency with a first signal to interference and noise ratio to a second transmission frequency with a second signal to interference and noise ratio, wherein the second signal to interference and noise ratio is lower than the first signal to interference and noise ratio. The method further includes selecting a transmission period based on a time when a least amount of signal noise is present on the transmission frequency and selecting an antenna pattern that reduces interference on the selected transmission frequency.

Abstract: A phased array antenna system includes an array of antennas having first antenna and second antennas disposed equidistantly from a third antenna. The first antenna is associated with a first gain and a first phase and the second antenna is associated with a second gain and a second phase. The first antenna receives a first reference signal corresponding to a calibration reference signal transmitted by the third antenna, and the second antenna receives a second reference signal corresponding to the calibration reference signal transmitted by the third antenna. The second receiver module is configured to adjust the second gain and the second phase associated with the second antenna to match the first gain and the first phase associated with the first antenna by comparing the first reference signal received by the first antenna with the second reference signal received by the second antenna.

Abstract: The method includes selecting, by control hardware, a first output from a phased locked loop, sending, by the control hardware, the first output from the phased locked loop to a first device under test and a second device under test, and adjusting, by the control hardware, a first phase rotator connected to the first device under test to a first rotator phase value of zero; determining a collection of phase detector values of a phase detector connected to the second device under test by adjusting a second phase rotator connected to the second device under test to sweep through a phase range and measuring the phase detector values of the phase detector; determining a phase detector gain of the phase detector by averaging the collection of phase detector values and storing, by the control hardware, the phase detector gain in memory hardware.

Abstract: A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic. Techniques for improving large signal performance for active shunt-peaked circuits are also disclosed.

Abstract: A synchronous circuit implements a bypass mode for use in conjunction with an inductive-capacitive (“LC”) buffer. The LC buffer receives differential conventional clock signals, and generates buffered differential conventional clock signals. A synchronous circuit, such as a latch, includes at least two clock receivers. The conventional clock signal is input to the first clock receiver, such as a transistor, and an auxiliary clock is input to a second clock receiver. The conventional clock signal provides timing for the synchronous circuit under a normal mode of operation, and the auxiliary clock signal provides timing for the synchronous circuit under a test mode of operation at a frequency lower than the conventional clock signal.

Abstract: A logic circuit employs a shunt peaked technique to enhance the switching speed of the circuit without an increase in power dissipation. A differential logic gate implements a digital circuit function. The shunt peaked logic circuit includes two resistive and two inductive elements. For each differential output line, a resistive element is coupled in series to an inductive element so as to couple the circuit power supply voltage to a differential output line. Under this configuration, the bandwidth of the logic circuit is increased without an increase in power consumption. The logic circuit may be implemented using CML or ECL logic.

Abstract: Methods and apparatus for buffering RF signals. A method includes receiving an input signal, wherein the input signal alternates between a first polarity and a second polarity. From the input signal, a first current is generated, wherein the first current is proportional to the input signal when the input signal has the first polarity, and approximately equal to zero when the input signal has the second polarity, and a second current is generated, wherein the second current is proportional to the input signal when the input signal has the second polarity, and approximately equal to zero when the input signal has the first polarity. A third current is generated proportional to the first current, and a fourth current is generated proportional to the second current. The first and fourth currents are applied to a first terminal of an inductor; and the second and third currents are applied to a second terminal of the inductor.

Abstract: A receiver for direct conversion of RF signals, a particular embodiment comprising a quadrature signal generation circuit having an oscillator with an oscillation frequency of ⅔ times that of the carrier frequency of the RF signal. For the particular embodiment, the quadrature generation circuit includes a divide-by-two division circuit to provide quadrature signals having a frequency of ⅓ that of the carrier frequency, and further including mixers and filters to mix the output of the oscillator and the output of the divide-by-two division circuit so as to provide quadrature signals at the carrier frequency.

Abstract: Methods and apparatus for buffering RF signals. A method includes receiving an input signal, wherein the input signal alternates between a first polarity and a second polarity. From the input signal, a first current is generated, wherein the first current is proportional to the input signal when the input signal has the first polarity, and approximately equal to zero when the input signal has the second polarity, and a second current is generated, wherein the second current is proportional to the input signal when the input signal has the second polarity, and approximately equal to zero when the input signal has the first polarity. A third current is generated proportional to the first current, and a fourth current is generated proportional to the second current. The first and fourth currents are applied to a first terminal of an inductor; and the second and third currents are applied to a second terminal of the inductor.