Abstract: A layer of doped or undoped germanosilicate glass is formed on a substrate and the layer of germanosilicate glass is thermally treated in steam to remove germanium from the germanosilicate glass, and thereby raise the reflow temperature of the germanosilicate glass so treated. The layer of germanosilicate glass on the substrate may be a nonplanar layer of germanosilicate glass. When thermally treating the nonplanar layer of germanosilicate glass in steam, the layer of germanosilicate glass may be planarized simultaneously with the removal of germanium from the planarized germanosilicate glass. This process may be repeated to create a hierarchy of reflowed glass where each underlying layer reflows at a higher temperature than the next deposited glass layer. The steam thermal treatment step may be preceded by a thermal pretreatment of the layer of germanosilicate glass in at least one of a noble gas and nitrogen gas, to reflow the layer of germanosilicate glass.

Abstract: A layer of doped or undoped germanosilicate glass is formed on a substrate and the layer of germanosilicate glass is thermally treated in steam to remove germanium from the germanosilicate glass, and thereby raise the reflow temperature of the germanosilicate glass so treated. The layer of germanosilicate glass on the substrate may be a nonplanar layer of germanosilicate glass. When thermally treating the nonplanar layer of germanosilicate glass in steam, the layer of germanosilicate glass may be planarized simultaneously with the removal of germanium from the planarized germanosilicate glass. This process may be repeated to create a hierarchy of reflowed glass where each underlying layer reflows at a higher temperature than the next deposited glass layer. The steam thermal treatment step may be preceded by a thermal pretreatment of the layer of germanosilicate glass in at least one of a noble gas and nitrogen gas, to reflow the layer of germanosilicate glass.

Abstract: A high performance integrated circuit chip package includes a support substrate having conductors extending from one face to the opposite face thereof and a multilayer wiring substrate on the opposite face of the support substrate for connecting chips mounted thereon to one another and to the conductors. A heat sink includes microchannels at one face thereof, with thermally conductive cushions connecting the one face of the heat sink with the exposed back sides of the chips, to provide a high density chip package with high heat dissipation. The support substrate and heat sink may be formed of blocks of material having thermal expansion matching silicon. The cushions are a low melting point solder, preferably pure indium, and are sufficiently thick to absorb thermal stresses, but sufficiently thin to efficiently conduct heat from the chips to the heat sink.

Abstract: A method of making a microsurgical cutter from a flat planar substrate having a top surface and a bottom surface comprises the steps of (a) forming a photoresist mask layer on the top surface in the pattern of the microsurgical instrument, the mask layer having an edge portion formed in a predetermined pattern therein; and then (b) etching isotropically the top surface of the substrate through the top surface to the bottom surface so that the top surface and bottom surface meet at a cutting edge portion, with the cutting edge portion having a configuration corresponding to the edge portion of the mask layer. The substrates may be formed from semiconductor materials such as silicon, silicon carbide, sapphire and diamond.

Abstract: A novel process for the selective deposition of solid-phase materials is disclosed, which process requires only the modulation of a single auxiliary gas within a suitable reactor assembly. According to the disclosed method, selective area deposition can be obtained on any desired microelectronic substrate by the creation of a vapor-phase chemical equilibrium system capable of deposition and etching the material to be deposited. The vapor-phase system is designed around a single reversible reaction wherein the material to be deposited equilibrates between that solid phase and its vapor-phase constituent species. By modulating an auxiliary gas flow into the reactor assembly, alternating deposition and etching processes can be obtained to yield an overall process which results in net overall selective and uniform deposition.

Abstract: A method of forming a high density semiconductor structure including one or more buried metal layers. One or more metal layers may be formed on a first semiconductor substrate, with the metal layer or layers being insulated from one another and from the substrate. One or more metal layers may be formed on the surface of a second substrate which may or may not be a semiconductor substrate. The topmost metal layers, either or both of which may have an insulating layer thereon, are placed in contact and heated in an oxidizing ambient atmosphere to form a bond therebetween. One or more vias connect the buried metal layers to the active devices in the substrates. The buried metal layers may form buried power and ground planes and buried metallization patterns for device interconnection.

Abstract: A thermally activated method of depositing a metal on a localized microscopic portion of a substrate, that can be carried out at relatively low process temperatures, and that is particularly useful for depositing metals in an amount and purity sufficient for electrical conductivity on substrates containing microelectronic circuits and devices or their respective precursors.

Abstract: An alternating cyclic (A.C.) method for selectively depositing materials, on the surface of a substrate without depositing the material on an adjacent mask layer. A gas of a reducible compound of the material and a reducing gas, preferably hydrogen, are simultaneously flowed through a reaction chamber to deposit the material on the substrate surface and to a lesser extent on the mask layer. Then, the flow of reducing gas is interrupted to cause the reducible compound gas to etch the material which forms on the mask layer in a disproportionation reaction. The deposition and etch steps are repeated in an alternating cyclic fashion until the requisite thickness is deposited. The process may take place in a single reaction chamber, using only the reducible compound gas and pulsed flow of the reducing gas.

Abstract: Ceramic parts may be bonded by forming bonding layers of silicon dioxide, silicon, metal or metal oxide on the parts, placing the bonding layers adjacent one another and heating in an oxidizing ambient atmosphere to form an oxide bond therebetween. Pressure may be applied between the ceramic parts to aid in bonding. A reliable bonded ceramic structure is thereby provided.

Abstract: A Maximum Areal Density Recessed Oxide Isolation (MADROX) process for forming semiconductor devices, in which forms an insulating layer is formed on a monocrystalline silicon substrate and a patterned polycrystalline silicon-containing layer is formed on the insulating layer. The substrate is then subjected to a low temperature plasma assisted oxidation to form recessed oxide isolation areas in the exposed regions of the substrate, with minimal encroachment under the patterned polycrystalline silicon-containing layer. The patterned polycrystalline silicon-containing layer acts as a mask, without itself being oxidized. Low temperature recessed oxide isolation regions may thereby be formed, without "bird's beak" formation. Maximum Areal Density Bipolar and Field Effect Transistor (MADFET) devices may be formed, using the patterned polycrystalline silicon-containing layer as a device contact if desired.

Abstract: An alternating cyclic (A.C.) method for selectively depositing single element semiconductor materials, on the surface of a substrate without depositing the material on an adjacent mask layer. A gas of a reducible compound of the material and a reducing gas, preferably hydrogen, are simultaneously flowed through a reaction chamber to deposit the material on the substrate surface and to a lesser extent on the mask layer. Then, the flow of reducing gas is interrupted to cause the reducible compound gas to etch the material which forms on the mask layer in a disproportionation reaction. The deposition and etch steps are repeated in an alternating cyclic fashion until the requisite thickness is deposited. The process may take place in a single reaction chamber, using only the reducible compound gas and pulsed flow of the reducing gas.

Abstract: A method of forming a high density semiconductor structure including one or more buried metal layers. One or more metal layers may be formed on a first semiconductor substrate, with the metal layer or layers being insulated from one another and from the substrate. One or more metal layers may be formed on the surface of a second substrate which may or may not be a semiconductor substrate. The topmost metal layers, either or both of which may have an insulating layer thereon, are placed in contact and heated in an oxidizing ambient atmosphere to form a bond therebetween. One or more vias connect the buried metal layers to the active devices in the substrates. The buried metal layers may form buried power and ground planes and buried metallization patterns for device interconnection.

Abstract: A method and resulting structure is disclosed in which a metal-to-metal bond is formed by heating the surfaces to be bonded in an oxidizing ambient atmosphere until the desired bond is achieved. Heating takes place at 700.degree. C.-1200.degree. C. and bonding may be enhanced by applying pressure between the surfaces while heating.

Abstract: A method of forming a nonsilicon semiconductor layer on an insulating layer by forming a thin heteroepitaxial layer of nonsilicon semiconductor on a first substrate having a lattice structure which matches that of the heteroepitaxial layer. A first insulating layer is formed on the heteroepitaxial layer. A second insulating layer is formed on the surface of a second substrate. The first and second insulating layers are bonded together to form a unified structure, and the first substate is etched away. In a preferred embodiment the heteroepitaxial layer is germanium, gallium arsenide or silicon-germanium alloy while the first substrate is silicon, germanium, gallium arsenide or silicon-germanium alloy.

Abstract: Apparatus for mounting a semiconductor device chip and making electrical connections thereto is disclosed. A semiconductor device chip has its backside connected to the surface of a substrate, and its upper surface includes a plurality of electrical pads across the entire surface thereof. A translator chip having a plurality of first electrical contacts disposed generally across the interior portion thereof are in electrical contact with the semiconductor device chip electrical pads, and a plurality of second electrical contacts disposed generally around the perimeter of the translator chip are electrically connected with the electrical terminals in the substrate to which the chip is attached. Heat may be removed from the semiconductor device chip through its backside via cooling channels in the substrate.

Abstract: A microelectronics apparatus and a method of fabricating customized connections between wiring planes superposed on a substrate is disclosed. A first wiring plane having multiple conductors is formed upon the substrate. An insulating layer is formed that overlies and electrically insulates the first wiring plane. A second wiring plane having multiple conductors is formed above the insulating layer by forming multiple conductors that are electrically connected to the first wiring plane with selected conductors of the first wiring plane being electrically connected to selected conductors of the second wiring plane. The connections may be modified by breaking selected ones of the electrical connections between the first and second wiring planes to customize the electrical interconnections.

Abstract: A microelectronics apparatus and a method of fabricating customized connections between wiring planes superposed on a substrate is disclosed. A first wiring plane having multiple conductors is formed upon the substrate. An insulating layer is formed that overlies and electrically insulates the first wiring plane. A second wiring plane having multiple conductors is formed above the insulating layer by forming multiple conductors that are electrically connected to the first wiring plane with selected conductors of the first wiring plane being electrically connected to selected conductors of the second wiring plane. The connections may be modified by breaking selected ones of the electrical connections between the first and second wiring planes to customize the electrical interconnections.

Abstract: A mirror array light valve is described comprising a transparent substrate, a plurality of post members arranged in a regular array on said substrate, and a plurality of deflectable square, rectangular, hexagonal or the like light-reflecting elements arranged in a regular array on said post members such that a post member is positioned under a corresponding corner of each element; methods for making the mirror array light valve are also described.

Abstract: A method and apparatus are disclosed for exposing photoresist using an incident electron beam during the fabrication of a semiconductor device. The method includes the steps of coating the substrate with a photoresist that is exposed in response to an electron beam. An electron beam is projected onto the photoresist and deflected to trace a pattern. The voltage and the amount of charge of the electron beam are controlled as it is deflected so that the energy incident upon the coated photoresist is correlated to variations in the photoresist thickness to expose the photoresist with minimal penetration therethrough to underlying structures.

Abstract: A heat dissipating system for cooling circuit chips or modules is described. The disclosed system includes circuit chips or modules which are vertically mounted, a gas at an elevated pressure being contained within an encased module for providing an enhanced thermal coupling between the chips or modules contained therein, and the walls of the encased module, whereby heat removal from the chips or modules is increased. This enhanced thermal coupling is combined with a reduction in the temperature of the walls of the encased modules so as to reduce the thermal resistance between the surrounding gas and the chips or modules to be cooled, whereby heat removal from the circuit chips or modules is substantially increased.