Abstract: A system and method for selecting a system for initializing a data processing system. A data processing system includes, a processor coupled to a memory via an interconnect and multiple systems for initializing the aforementioned data processing system. A multiplexor is also included to select between multiple initialization systems. In the method of initializing a data processing system, an initialization or reset command is received from an external reset circuit or the processor; at least one selector signal is generated; and a set of initialization data from a selected initialization system is utilized to initialize the data processing system.

Abstract: A system and method for selecting a system for initializing a data processing system. A data processing system includes, a processor coupled to a memory via an interconnect and multiple systems for initializing the aforementioned data processing system. A multiplexor is also included to select between multiple initialization systems. In the method of initializing a data processing system, an initialization or reset command is received from an external reset circuit or the processor; at least one selector signal is generated; and a set of initialization data from a selected initialization system is utilized to initialize the data processing system.

Abstract: A memory and memory architecture for use by a processor executing real time code and a system on a chip including the processor and memory containing the code. An effective address is maintained in a cache directory. In the preferred embodiment memory, individual functions are loaded into physical memory at permanently selected locations and selected by the effective address in the cache directory. By preselecting task storage locations, system performance may be tuned or optimized to assure predictable performance or task execution.

Abstract: A computer system includes a processor and a cache and memory management unit. The processor includes a means for retiring instructions in program order. The cache and memory management unit includes means for detecting when a translation has been evicted from a lookaside buffer and means for communicating eviction information to the means for retiring instructions in program order. The means for retiring instructions in program order includes means for holding a storage related instruction which causes a miss in the lookaside buffer or in the cache in a first pass of execution until the instruction becomes the oldest storage related instruction in program sequence and further includes means responsive to the eviction information for flushing all storage related instructions except the current storage related instruction. The system avoids the occurrence of misses in the buffer late in execution (e.g., PASS 2 or later), thus avoiding a necessity for complex recovery provisions.