Abstract: An initial operating speed of a cooling fan at an information handling system is determined. A microphone is located at the system to favor acquisition of ambient sound relative to acquisition of sound emanating from the cooling fan. An audio signal is received from the microphone. The operating speed of the cooling fan is adjusted based on a level of the audio signal.

Abstract: An information handling system port selectively communicates differential and single-ended signals from port pins to a cable coupled with the port so that bandwidth of information sent through the port increases if a cable accepts single-ended signals. Single-ended signals sent from the port pins are provided to a redriver of the cable to generate differential signals on wireline pairs of the cable. The redriven single-ended signals effectively double the bandwidth from reconfigured differential pairs of a port without increasing the port footprint or altering the port from a standard form factor, such as a Type-C USB form factor.

Abstract: An information handling system port selectively communicates differential and single-ended signals from port pins to a cable coupled with the port so that bandwidth of information sent through the port increases if a cable accepts single-ended signals. Single-ended signals sent from the port pins are provided to a redriver of the cable to generate differential signals on wireline pairs of the cable. The redriven single-ended signals effectively double the bandwidth from reconfigured differential pairs of a port without increasing the port footprint or altering the port from a standard form factor, such as a Type-C USB form factor.

Abstract: An initial operating speed of a cooling fan at an information handling system is determined. A microphone is located at the system to favor acquisition of ambient sound relative to acquisition of sound emanating from the cooling fan. An audio signal is received from the microphone. The operating speed of the cooling fan is adjusted based on a level of the audio signal.

Abstract: A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.

Abstract: A system and method for provisioning within a system design to allow the storage and IO resources to scale with compute resources are provided.

Abstract: The need for a SAF-TE processor embedded on a SCSI backplane of a hot-swap hard disk drive enclosure is eliminated by utilizing the functionality of a RAID on motherboard (ROMB) controller and an Embedded Server Management (ESM) interface already present in an information handling system. Only sensors and input-output (I/O) registers remain on the SCSI backplane as required. The SCSI backplane I/O is split between the ESM and ROMB according to functional requirements.

Abstract: When a power supply is turned off its output voltages decrease over certain times. If the power supply is turned back on before the output voltages have had time to decrease to a level required by certain electronic circuits before power is reapplied, then these electronic circuits may malfunction or latch-up. A power supply shutdown control monitors voltage levels of the power supply. The power supply shutdown control prevents the power supply from being turned back on before the output voltages have reached a sufficiently low voltage level. A voltage reset monitor determines when a power supply voltage drops below a certain level, and then a memory device stores the instance of a power supply voltage drop and uses the stored instance to prevent the power supply from being turned on until the monitored voltage(s) have reached the sufficiently low voltage level. Then, the stored instance is reset and the power supply may be re-energized.

Abstract: The need for a SAF-TE processor embedded on a SCSI backplane of a hot-swap hard disk drive enclosure is eliminated by utilizing the functionality of a RAID on motherboard (ROMB) controller and an Embedded Server Management (ESM) interface already present in an information handling system. Only sensors and input-output (I/O) registers remain on the SCSI backplane as required. The SCSI backplane I/O is split between the ESM and ROMB according to functional requirements.

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2).times.(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle.

Abstract: An apparatus for conditioning signals output from a computer system expansion card to a computer system board to test system board bus specifications and timing limits. The apparatus comprises two signal conditioning extension cards which are used to condition signals from a slave card and a bus master card. The signal conditioning extension cards according to the present invention are interposed between the bus master or slave expansion card and the system board and selectively advance or delay the signals output from the expansion card to the system board. The slave signal conditioning card also selectively delays the read data valid window of the slave card to test the limits of the system board. The bus master signal conditioning card selectively delays the write data valid window of the bus master card to test the limits of the system board.

Abstract: A system where counters which increment based on a desired data transfer width are used to control addresses provided to memory devices. Transceivers are located on each byte lane between the system data bus and the internal data bus, with copy transceivers connected between the various byte lanes of the internal bus. The various devices are controlled so that data can be transferred in one, two or four byte increments and yet the memory devices are fully utilized. Separate counters are used for read and write directions. Circuitry is used to determine system memory data width and addressing format so that the desired data transfer width can be determined and set to allow the highest possible data transfer rate.