Abstract: The present application relates to a system and a method for determining relative positions slave units along a stub bus with at least a power line and a ground line. Each slave unit is operable in different power modes, which are differentiated by effective resistances between the power and ground lines. A reference voltage potential drop is determined for each slave unit while the slave units are operating in a first power mode. A positioning voltage potential drop is determined for one or more slave units while a selected slave unit is operating in a second power mode. Relative positions of the slave units are determined based on the relative voltage potential drops obtained from the reference and positioning voltage potential drops.

Abstract: An example embodiment is directed to a voltage regulation circuit. The voltage regulation circuit comprises a first control loop and a second control loop that are separately activatable. The first control loop regulates an output current provided to an output terminal, and the second control loop regulates an output voltage provided to the output terminal. The voltage regulation circuit further includes a mode switching circuit that switches operation between the first and the second control loops by separately activating one of the first and second control loops and deactivating the other in response to a fault condition at the output terminal at which a regulated load is connectable.

Abstract: A control circuit provides a signal to a control terminal of the transistor to control the conductivity of the transistor. The control circuit includes a voltage-to-current converter that provides an indication of the control terminal-to-current terminal voltage of a transistor. The control circuit includes control circuitry that uses the indication from the voltage-to-current converter in controlling the current applied to the control terminal.

Abstract: The present application relates to a system and a method for determining relative positions slave units along a stub bus with at least a power line and a ground line. Each slave unit is operable in different power modes, which are differentiated by effective resistances between the power and ground lines. A reference voltage potential drop is determined for each slave unit while the slave units are operating in a first power mode. A positioning voltage potential drop is determined for one or more slave units while a selected slave unit is operating in a second power mode. Relative positions of the slave units are determined based on the relative voltage potential drops obtained from the reference and positioning voltage potential drops.

Abstract: An overvoltage protection circuit is disclosed. The overvoltage protection circuit includes an input voltage port, an output voltage port, a low pass filter coupled to the input voltage port and a voltage regulator coupled to the low pass filter. The overvoltage protection circuit also includes a transistor having a gate, a drain and a source. The transistor is coupled to the input voltage port and the output voltage port and the gate is coupled to the voltage regulator.

Abstract: Disclosed is a controller for controlling a string of N LEDs connected in series and each having a current bypass switch in parallel therewith and configured to be supplied from a current source connected in series with the string of LEDs and being supplied by a supply voltage, the controller comprising: a respective bypass switch controller for each bypass switch and configured to control the respective bypass switch such that the respective LED has an on-period and an off-period, according to a common duty cycle; a phase control unit configured to set a respective timing of each of the bypass switches such that the fraction of LEDs not bypassed corresponds to the duty cycle; and a duty cycle adjustor configured to adjust the duty cycle, in dependence on the supply voltage. Associated methods and circuits are also disclosed.

Abstract: Disclosed is a controller for controlling a string of N LEDs connected in series and each having a current bypass switch in parallel therewith and configured to be supplied from a current source connected in series with the string of LEDs and being supplied by a supply voltage, the controller comprising: a respective bypass switch controller for each bypass switch and configured to control the respective bypass switch such that the respective LED has an on-period and an off-period, according to a common duty cycle; a phase control unit configured to set a respective timing of each of the bypass switches such that the fraction of LEDs not bypassed corresponds to the duty cycle; and a duty cycle adjustor configured to adjust the duty cycle, in dependence on the supply voltage. Associated methods and circuits are also disclosed.

Abstract: An overvoltage protection circuit is disclosed. The overvoltage protection circuit includes an input voltage port, an output voltage port, a low pass filter coupled to the input voltage port and a voltage regulator coupled to the low pass filter. The overvoltage protection circuit also includes a transistor having a gate, a drain and a source. The transistor is coupled to the input voltage port and the output voltage port and the gate is coupled to the voltage regulator.

Abstract: Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.

Abstract: In accordance with one or more example aspects of the disclosure, communications are effected on a bus using bit time and slew rate feedback. As consistent with one or more embodiments, communications are effected in a network including a master circuit and a plurality of slave circuits, on bus that is controlled by the master circuit corresponding to master and slave data communication. A feedback signal is provided, which is indicative of a slew rate and bit time of signals communicated between the master and slave circuits on the bus. Data is transmitted on the bus by generating output signals via a waveform corresponding to an input signal, and controlling the waveform based upon the slew rate and bit time indicated via the feedback signal.

Abstract: Embodiments of digital-to-analog converters (DACs), methods for operating a DAC, and transceiver circuits are described. In one embodiment, a DAC includes an input terminal configured to receive a digital signal, a converter circuit configured to convert the digital signal into an analog signal using first-order interpolation allowing low electromagnetic emissions, and an output terminal configured to output the analog signal. Other embodiments are also described.

Abstract: Embodiments of transceiver circuits and methods for operating a transceiver circuit are described. In one embodiment, a transceiver circuit includes a feedback loop connected to a bus and a control circuit connected to the bus. The feedback loop includes a tunable low-pass filter. The control circuit is configured to detect a radio frequency (RF) disturbance on the bus and control the bandwidth of the tunable low-pass filter in response to detection of the RF disturbance on the bus. Other embodiments are also described.

Abstract: In accordance with one or more example aspects of the disclosure, communications are effected on a bus using bit time and slew rate feedback. As consistent with one or more embodiments, communications are effected in a network including a master circuit and a plurality of slave circuits, on bus that is controlled by the master circuit corresponding to master and slave data communication. A feedback signal is provided, which is indicative of a slew rate and bit time of signals communicated between the master and slave circuits on the bus. Data is transmitted on the bus by generating output signals via a waveform corresponding to an input signal, and controlling the waveform based upon the slew rate and bit time indicated via the feedback signal.

Abstract: A high voltage electrical switch including: a plurality of series connected semiconductor switches; a plurality of rectifiers wherein each rectifier is connected to a semiconductor switch control input of one of the semiconductor switches; a radio frequency signal generator; and a plurality of galvanic isolators, wherein each galvanic isolator connects the radio frequency signal generator to one of the plurality of rectifiers, wherein the plurality of semiconductor switches are isolated from one another.

Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.

Abstract: A high voltage electrical switch including: a plurality of series connected semiconductor switches; a plurality of rectifiers wherein each rectifier is connected to a semiconductor switch control input of one of the semiconductor switches; a radio frequency signal generator; and a plurality of galvanic isolators, wherein each galvanic isolator connects the radio frequency signal generator to one of the plurality of rectifiers, wherein the plurality of semiconductor switches are isolated from one another.

Abstract: A method for frequency acquisition comprising steps of, acquiring samples of an input signal, each sample having edges, making sets with a fixed number of consecutively taken samples, numbering the edges in each set and determining a number of edges, comparing the number of edges in each set with an expected number of edges in the sets, increasing a frequency of a reference oscillator used in acquiring samples if the actual number of edges exceeds the expected number of edges, and decreasing the frequency of the reference oscillator used in acquiring samples if the expected number of edges exceeds the actual number of edges in a set.

Abstract: A multi-phase clock and data recovery circuit system including a voltage controlled oscillator including plural identical structural cells coupled in a ring, the voltage controlled oscillator providing plural phased shifted signals having the same frequency. The circuit further includes a feedback loop including plural data samplers adapted to receive the plural phase shifted signals provided by the voltage controlled oscillator and a phase detector coupled to coupled to a phase alignment circuit receiving output signals generated by the plural data samplers and generating control signals to the voltage controlled oscillator at a bit rate of the input signal.