Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

Abstract: A resistive divider circuit for differential signaling is disclosed. The resistive divider includes a first branch and a second branch and each branch has an input, a first resistive component comprised of a number of unit resistors, a second resistive component comprised of a number of unit resistors, and an output connected between the first resistive component and the second resistive component, the output forming a differential mode output. The first resistive component and the second resistive component are comprised of an equal number of unit resistors.

Abstract: Disclosed is a differential driver circuit including an input module to receive an input signal and split the input signal into high and low components, a first level shifter to receive the high signal component and output a high side input signal to a high side driver, a delay module to receive the low signal component and output a low side input signal to a low side driver, and a multi-voltage domain phase detector to measure a phase difference between the high side input signal and the low side input signal to provide feedback to the input module and output a phase adjusted output signal to match a first delay timing of the first level shifter.

Abstract: A resistive divider circuit for differential signaling is disclosed. The resistive divider includes a first branch and a second branch and each branch has an input, a first resistive component comprised of a number of unit resistors, a second resistive component comprised of a number of unit resistors, and an output connected between the first resistive component and the second resistive component, the output forming a differential mode output. The first resistive component and the second resistive component are comprised of an equal number of unit resistors.

Abstract: A frequency divider (200; 300; 400) configured to receive a plurality of oscillating signals (202; 302; 402) and generate output signalling (204; 310; 410). The frequency divider comprises an enable signalling generator (206) configured to process the plurality of oscillating signals (202; 302; 402) and generate enable signalling (210; 314) representative of which of the oscillating signals (202; 302; 402) is to be used to derive the output signalling (204; 310; 410). The frequency divider also comprises an output signal selector (208; 308; 408) configured to process one or more of the oscillating signals (202; 302; 402) and the enable signalling (210; 314) such that an oscillating signal (202; 302; 402) is provided as the output signalling (204; 310; 410) of the frequency divider in accordance with the enable signalling (210; 314).