Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a tile through wire twisting or through via connections and wires in another metal layer. Wires that change tracks may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires compared to the signal transition in conventional interconnect circuitry. At the same time, sub-optimal wire stitching in a routing tile that connects a wire that ends in the next routing tile to a wire that starts in the routing tile, whereby the two wires overlap each other may enable beneficial crosstalk, which may further improve signal transition time.

Abstract: An integrated circuit may include a first logic region having a first bidirectional driver circuit and a second logic region having a logic circuit and a second bidirectional circuit. The first bidirectional driver circuit may be coupled to the second bidirectional driver circuit via a conductive path. The second bidirectional circuit may receive a dynamic control signal from the logic circuit to selectively transmit a signal to the first bidirectional driver circuit based on the dynamic control signal. The first logic region further includes an additional logic circuit. The additional logic circuit may provide an additional dynamic control signal to the first bidirectional driver circuit to selectively transmit an additional signal to the second bidirectional driver circuit over the conductive path. To prevent current contention, only one bidirectional driver circuit may be activated to drive the conductive path at a given time.

Abstract: An integrated circuit may have interconnect circuitry which may include a sequence of tiles. Each tile may be associated with a given tile type, and each tile type may include a predetermined routing of multiple wires on multiple tracks. Wires may change tracks within a given tile, which is sometimes also referred to as wire twisting. Wire twists may reduce the overlap between pairs of adjacent wires, thereby reducing the coupling capacitance between the respective wires. Reducing the coupling capacitance may result in reduced crosstalk between the wires which may speed up the signal transition along those wires. At the same time, the twist region height (i.e., the region in the tile in which wires are twisted) may be reduced compared to conventional interconnect circuitry.