Patents by Inventor Aron Lunde
Aron Lunde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8509016Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.Type: GrantFiled: March 14, 2012Date of Patent: August 13, 2013Assignee: Micron Technology, Inc.Inventors: Aron Lunde, Seth Eichmeyer, Tim Cowles, Patrick Mullarkey
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Publication number: 20120176851Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.Type: ApplicationFiled: March 14, 2012Publication date: July 12, 2012Applicant: Micron Technology, IncInventors: Aron Lunde, Seth Eichmeyer, Tim Cowles, Patrick Mullarkey
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Patent number: 8144534Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.Type: GrantFiled: August 25, 2009Date of Patent: March 27, 2012Assignee: Micron Technology, Inc.Inventors: Aron Lunde, Seth Eichmeyer, Tim Cowles, Patrick Mullarkey
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Publication number: 20110051538Abstract: Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.Type: ApplicationFiled: August 25, 2009Publication date: March 3, 2011Applicant: Micron Technology, Inc.Inventors: Aron Lunde, Seth Eichmeyer, Tim Cowles, Patrick Mullarkey
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Patent number: 7251173Abstract: A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.Type: GrantFiled: August 2, 2005Date of Patent: July 31, 2007Assignee: Micron Technology, Inc.Inventors: Aron Lunde, Michael Shore
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Publication number: 20070030742Abstract: A column redundancy system combining at least two different redundancy systems to provide local redundant memory and shared redundant memory. The column redundancy system includes a plurality of sets of local redundant columns memory, each set of local redundant columns of memory is associated with a corresponding one of a plurality of memory sub-arrays. The columns of memory of the sets of local redundant columns of memory are adapted to replace defective columns of memory of the respective memory sub-arrays. The column redundancy system further includes columns of shared redundant memory that are adapted to replace defective columns of memory of the plurality of memory sub-arrays.Type: ApplicationFiled: August 2, 2005Publication date: February 8, 2007Inventors: Aron Lunde, Michael Shore
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Publication number: 20060131577Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.Type: ApplicationFiled: January 24, 2006Publication date: June 22, 2006Inventors: Timothy Cowles, Aron Lunde
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Publication number: 20060113535Abstract: A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence.Type: ApplicationFiled: January 12, 2006Publication date: June 1, 2006Applicant: Micron Technology, Inc.Inventor: Aron Lunde
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Publication number: 20050099862Abstract: A semiconductor substrate, probe card, and methods for stressing and testing dies on a semiconductor substrate are provided. The semiconductor substrate, typically a semiconductor wafer, comprises dies disposed thereon and a redistribution layer (RDL) for routing signals from a test circuit into dies on the substrate that are not currently under probe. The RDL includes look-ahead contacts associated with a first die set that are electrically connected by traces to dies of a second die set. Upon contact of elements of the probe tester with the look-ahead contacts, required Vcc power, GND ground potential and signals from the probe tester are routed through the traces to the die of the die set not currently under probe. The dies can comprise a built-in self-stress (BISS) circuit and/or a built-in self-test (BIST) circuit for implementing a stress or test sequence.Type: ApplicationFiled: September 3, 2003Publication date: May 12, 2005Inventor: Aron Lunde
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Publication number: 20050059175Abstract: A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The wafer is subjected to testing to identify functional and nonfunctional dice. The locations of the functional dice are analyzed to determine the location of immediately adjacent or closely proximate functional dice. A group of functional dice is identified and an interconnection circuit is formed therebetween. The functional die group, once interconnected, is then segmented from the wafer while maintaining the unitary integrity of the functional die group as well as the associated interconnections between dice. Modules including one or more functional die groups and methods of fabricating functional die groups and modules are also disclosed.Type: ApplicationFiled: August 20, 2004Publication date: March 17, 2005Inventors: Aron Lunde, Kevin Duesman, Timothy Cowles
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Publication number: 20050056945Abstract: A semiconductor wafer or other bulk semiconductor substrate having a plurality of dice thereon is manufactured using conventional processing techniques. The wafer is subjected to testing to identify functional and nonfunctional dice. The locations of the functional dice are analyzed to determine the location of immediately adjacent or closely proximate functional dice. A group of functional dice is identified and an interconnection circuit is formed therebetween. The functional die group, once interconnected, is then segmented from the wafer while maintaining the unitary integrity of the functional die group as well as the associated interconnections between dice. Modules including one or more functional die groups and methods of fabricating functional die groups and modules are also disclosed.Type: ApplicationFiled: September 16, 2003Publication date: March 17, 2005Inventors: Aron Lunde, Kevin Duesman, Timothy Cowles
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Publication number: 20050026315Abstract: An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.Type: ApplicationFiled: August 30, 2004Publication date: February 3, 2005Inventors: Timothy Cowles, Aron Lunde