Abstract: Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.

Abstract: Disclosed is a method, a circuit arrangement, and an electronic circuit. The method includes discharging a gate-source capacitance of a transistor device from a first voltage level to a second voltage level with a first resistor connected in parallel with the gate-source capacitance and measuring a first discharging time associated with the discharging, and discharging the gate-source capacitance from the first voltage level to the second voltage level with the first resistor and a second resistor connected in parallel with the gate-source capacitance and measuring a second discharging time associated with the discharging. The method further includes comparing a ratio between the first discharging time and the second discharging time with a predefined threshold, and detecting a fault based on the comparing.

Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

Abstract: A testing device in accordance with various embodiments may include: a plurality of first terminals configured to be connected to a plurality of devices-under-test, wherein each first terminal of the plurality of first terminals may be configured to be connected to a respective device-under-test of the plurality of devices-under-test; a signal interface configured to be connected to a tester; and a circuit configured to exchange an identical first signal with each device-under-test of the plurality of devices-under-test through a respective first terminal of the plurality of first terminals, and to exchange at least one interface signal with the tester through the signal interface.

Abstract: One aspect is a circuit arrangement having a load current path with a load transistor having a first and a second load path terminal and a control terminal. A first measurement current path includes a measuring transistor having a first and a second load path terminal and a control terminal. The control terminals and first load path terminals of the load transistor and the measuring transistor are coupled. A first regulating circuit has a controllable resistor and is designed to drive the resistor depending on electrical potentials at the second load path terminals of the load transistor and of the measuring transistor. A current mirror circuit is coupled between the first measurement current path and a second measurement current path. A deactivation circuit is designed to deactivate the first regulating circuit depending on a current flowing through the measuring transistor.

Abstract: One aspect is a circuit arrangement having a load current path with a load transistor having a first and a second load path terminal and a control terminal. A first measurement current path includes a measuring transistor having a first and a second load path terminal and a control terminal. The control terminals and first load path terminals of the load transistor and the measuring transistor are coupled. A first regulating circuit has a controllable resistor and is designed to drive the resistor depending on electrical potentials at the second load path terminals of the load transistor and of the measuring transistor. A current mirror circuit is coupled between the first measurement current path and a second measurement current path. A deactivation circuit is designed to deactivate the first regulating circuit depending on a current flowing through the measuring transistor.