Patents by Inventor Arpan Mahorowala
Arpan Mahorowala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11987876Abstract: Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.Type: GrantFiled: March 14, 2019Date of Patent: May 21, 2024Assignee: Lam Research CorporationInventors: Sivananda Krishnan Kanakasabapathy, Hui-Jung Wu, Richard Wise, Arpan Mahorowala
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Publication number: 20240030031Abstract: Thin tin oxide films can be used in semiconductor device manufacturing. In one implementation, a method of processing a semiconductor substrate includes: providing a semiconductor substrate having a plurality of protruding features residing on an etch stop layer material, and an exposed tin oxide layer in contact with both the protruding features and the etch stop layer material, where the tin oxide layer covers both sidewalls and horizontal surfaces of the protruding features; and then completely removing the tin oxide layer from horizontal surfaces of the semiconductor substrate without completely removing the tin oxide layer residing at the sidewalls of the protruding features. Next, the protruding features can be removed without completely removing the tin oxide layer that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers.Type: ApplicationFiled: October 6, 2023Publication date: January 25, 2024Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. Van Schravendijk
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Patent number: 11183383Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.Type: GrantFiled: March 20, 2020Date of Patent: November 23, 2021Assignee: Lam Research CorporationInventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick van Cleemput, Bart J. van Schravendijk
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Patent number: 11031245Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.Type: GrantFiled: September 22, 2017Date of Patent: June 8, 2021Assignee: Lan Research CorporationInventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
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Publication number: 20210017643Abstract: Methods and apparatuses for processing semiconductor substrates in an integration scheme to form chamferless vias are provided herein. Methods include bifurcating etching of dielectric by depositing a conformal removable sealant layer having properties for selective removal relative to dielectric material without damaging dielectric material. Some methods include forming an ashable conformal sealant layer. Methods also include forming hard masks including a Group IV metal and removing conformal removable sealant layers and hard masks in one operation using same etching chemistries.Type: ApplicationFiled: March 14, 2019Publication date: January 21, 2021Inventors: Sivananda Krishnan Kanakasabapathy, Hui-Jung Wu, Richard Wise, Arpan Mahorowala
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Publication number: 20200219725Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.Type: ApplicationFiled: March 20, 2020Publication date: July 9, 2020Applicant: Lam Research CorporationInventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick van Cleemput, Bart J. van Schravendijk
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Publication number: 20190131130Abstract: Methods of and apparatuses for processing a metal oxide film are provided. Methods involve (a) exposing the metal oxide film to a boron halide reactant and igniting a first plasma with a first bias power to modify a surface of the metal oxide film, and (b) exposing the modified surface of the metal oxide film to a second plasma at a second bias power and for a duration sufficient to remove the modified surface without sputtering. Methods also involve (c) selectively depositing a metal oxide material on the metal oxide film to fill crevices within the metal oxide film.Type: ApplicationFiled: October 31, 2017Publication date: May 2, 2019Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Dennis M. Hausmann
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Publication number: 20180308687Abstract: Process and apparatus for forming a negative patterning mask in the context of EUV patterning uses a selective deposition process to deposit a metal oxide or metal nitride thin film in a feature defined in an EUV resist to prepare a negative image for patterning. The method to produce the “negative” image does not involve an etch back step and therefore accommodates the small resist budget. The material forming the “negative” image is significantly more etch resistant than resist which eliminates the need for an additional hard mask transfer layer.Type: ApplicationFiled: April 24, 2017Publication date: October 25, 2018Inventors: David Charles Smith, Arpan Mahorowala
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Patent number: 10074543Abstract: Methods and apparatuses for depositing low density spacers using atomic layer deposition for negative patterning schemes are provided herein. Methods involve one or more of: (1) exposing a substrate to a plasma for a duration less than about 300 ms in each cycle of alternating pulses of a deposition precursor and oxidizing plasma; (2) exposing the substrate to the plasma at a radio frequency power density of less than about 0.2 W/cm2; and (3) exposing the substrate to the plasma produced from a process gas having an argon to oxidant ratio of at least about 1:12.Type: GrantFiled: August 31, 2016Date of Patent: September 11, 2018Assignee: Lam Research CorporationInventors: Arpan Mahorowala, Ishtak Karim, Purushottam Kumar, Shankar Swaminathan, Adrien LaVoie
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Publication number: 20180061650Abstract: Methods and apparatuses for depositing low density spacers using atomic layer deposition for negative patterning schemes are provided herein. Methods involve one or more of: (1) exposing a substrate to a plasma for a duration less than about 300 ms in each cycle of alternating pulses of a deposition precursor and oxidizing plasma; (2) exposing the substrate to the plasma at a radio frequency power density of less than about 0.2 W/cm2; and (3) exposing the substrate to the plasma produced from a process gas having an argon to oxidant ratio of at least about 1:12.Type: ApplicationFiled: August 31, 2016Publication date: March 1, 2018Inventors: Arpan Mahorowala, Ishtak Karim, Purushottam Kumar, Shankar Swaminathan, Adrien LaVoie
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Publication number: 20180012759Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Inventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
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Patent number: 9824893Abstract: Thin tin oxide films are used as spacers in semiconductor device manufacturing. In one implementation, thin tin oxide film is conformally deposited onto a semiconductor substrate having an exposed layer of a first material (e.g., silicon oxide or silicon nitride) and a plurality of protruding features comprising a second material (e.g., silicon or carbon). For example, 10-100 nm thick tin oxide layer can be deposited using atomic layer deposition. Next, tin oxide film is removed from horizontal surfaces, without being completely removed from the sidewalls of the protruding features. Next, the material of protruding features is etched away, leaving tin oxide spacers on the substrate. This is followed by etching the unprotected portions of the first material, without removal of the spacers. Next, underlying layer is etched, and spacers are removed. Tin-containing particles can be removed from processing chambers by converting them to volatile tin hydride.Type: GrantFiled: June 28, 2016Date of Patent: November 21, 2017Assignee: Lam Research CorporationInventors: David Charles Smith, Richard Wise, Arpan Mahorowala, Patrick A. Van Cleemput, Bart J. van Schravendijk
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Patent number: 7344991Abstract: A method for etching an organic anti-reflective coating (ARC) layer on a substrate in a plasma processing system comprising: introducing a process gas comprising ammonia (NH3), and a passivation gas; forming a plasma from the process gas; and exposing the substrate to the plasma. The process gas can, for example, constitute NH3 and a hydrocarbon gas such as at least one of C2H4, CH4, C2H2, C2H6, C3H4, C3H6, C3H8, C4H6, C4H8, C4H10, C5H8, C5H10, C6H6, C6H10, and C6H12. Additionally, the process chemistry can further comprise the addition of helium. The present invention further presents a method for forming a bilayer mask for etching a thin film on a substrate, wherein the method comprises: forming the thin film on the substrate; forming an ARC layer on the thin film; forming a photoresist pattern on the ARC layer; and transferring the photoresist pattern to the ARC layer with an etch process using a process gas comprising ammonia (NH3), and a passivation gas.Type: GrantFiled: August 14, 2003Date of Patent: March 18, 2008Assignee: Tokyo Electron LimitedInventors: Vaidyanathan Balasubramaniam, Koichiro Inazawa, Rich Wise, Arpan Mahorowala, Siddhartha Panda
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Publication number: 20070196748Abstract: A lithographic structure consisting essentially of: an organic antireflective material disposed on a substrate; a vapor-deposited RCHX material, wherein R is one or more elements selected from the group consisting of Si, Ge, B, Sn, Fe and Ti, and wherein X is not present or is one or more elements selected from the group consisting of O, N, S and F; and a photoresist material disposed on the RCHX material. The invention is also directed to methods of making the lithographic structure, and using the structure to pattern a substrate.Type: ApplicationFiled: February 17, 2006Publication date: August 23, 2007Applicant: International Business Machines CorporationInventors: Marie Angelopoulos, Katherina Babich, Sean Burns, Richard Conti, Allen Gabor, Scott Halle, Arpan Mahorowala, Dirk Pfeiffer
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Publication number: 20070105363Abstract: Antireflective hardmask compositions and techniques for the use of antireflective hardmask compositions for processing of semiconductor devices are provided. In one aspect of the invention, an antireflective hardmask layer for lithography is provided. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component. In another aspect of the invention, a method for processing a semiconductor device is provided. The method comprises the steps of: providing a material layer on a substrate; forming an antireflective hardmask layer over the material layer. The antireflective hardmask layer comprises a carbosilane polymer backbone comprising at least one chromophore moiety and at least one transparent moiety; and a crosslinking component.Type: ApplicationFiled: December 21, 2006Publication date: May 10, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Katherina Babich, Elbert Huang, Arpan Mahorowala, David Medeiros, Dirk Pfeiffer, Karen Temple
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Publication number: 20070015083Abstract: An antireflective composition and a lithographic structure comprising a silicon-metal oxide, antireflective material derived from the composition. The antireflective composition comprises a polymer of formula I, wherein 1?x?2; 1?y?5; 1?0; m>0; n>0; R is a chromophore, M is a metal selected from Group IIIB to Group VIB, lanthanides, Group IIIA, Group IVA except silicon; and L is an optional ligand. The invention is also directed to a process of making a lithographic structure including a silicon-metal oxide, antireflective material.Type: ApplicationFiled: July 14, 2005Publication date: January 18, 2007Applicant: International Business Machines CorporationInventors: Katherina Babich, Sean Burns, Elbert Huang, Arpan Mahorowala, Dirk Pfeiffer, Karen Temple
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Publication number: 20070015082Abstract: A lithographic structure comprising: an organic antireflective material disposed on a substrate; and a silicon antireflective material disposed on the organic antireflective material. The silicon antireflective material comprises a crosslinked polymer with a SiOx backbone, a chromophore, and a transparent organic group that is substantially transparent to 193 nm or 157 nm radiation. In combination, the organic antireflective material and the silicon antireflective material provide an antireflective material suitable for deep ultraviolet lithography. The invention is also directed to a process of making the lithographic structure.Type: ApplicationFiled: July 14, 2005Publication date: January 18, 2007Applicant: International Business Machines CorporationInventors: Marie Angelopoulos, Katherina Babich, Sean Burns, Allen Gabor, Scott Halle, Arpan Mahorowala, Dirk Pfeiffer
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Publication number: 20060154184Abstract: A method of patterning a feature in a substrate to reduce edge roughness comprises forming a resist layer overlying a substrate, exposing the resist layer to create an image of a feature, and developing the exposed resist layer to leave a portion of the resist layer that creates the image of the feature. The method then includes treating the exposed resist layer with a plasma to cure the portion of the resist layer creating the feature image. The plasma treatment has an ion bombardment level insufficient to substantially etch the underlying substrate. The method then includes etching the underlying substrate to create the feature.Type: ApplicationFiled: January 12, 2005Publication date: July 13, 2006Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.Inventors: Arpan Mahorowala, Scott Bell, S. Dakshina Murthy, Stacy Rasgon, Hongwen Yan, Chih-Yuh Yang
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Publication number: 20060118785Abstract: Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.Type: ApplicationFiled: January 23, 2006Publication date: June 8, 2006Applicant: International Business Machines CorporationInventors: Scott Allen, Katherina Babich, Steven Holmes, Arpan Mahorowala, Dirk Pfeiffer, Richard Wise
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Publication number: 20060049139Abstract: A method and system is described for etching a tunable etch resistant anti-reflective (TERA) coating. The TERA coating can be utilized, for example, as a hard mask, or as an anti-reflective coating for complementing a lithographic structure. The TERA coating can include a structural formula R:C:H:X, wherein R is selected from the group consisting of Si, Ge, B, Sn, Fe, Ti, and combinations thereof, and wherein X is not present or is selected from the group consisting of one or more of O, N, S, and F. During the formation of a structure in a film stack, a pattern is transferred to the TERA coating using dry plasma etching having a SF6-based etch chemistry.Type: ApplicationFiled: August 26, 2004Publication date: March 9, 2006Applicants: Tokyo Electron Limited, International Business Machines CorporationInventors: Annie Xia, Hiromasa Mochiki, Arpan Mahorowala