Patents by Inventor Arrvindh Shriraman

Arrvindh Shriraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9411733
    Abstract: A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: August 9, 2016
    Assignee: University of Rochester
    Inventors: Hongzhou Zhao, Arrvindh Shriraman, Sandhya Dwarkadas
  • Patent number: 8661204
    Abstract: The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: February 25, 2014
    Assignee: University of Rochester, Office of Technology Transfer
    Inventors: Sandhya Dwarkadas, Arrvindh Shriraman, Michael Scott
  • Publication number: 20140032848
    Abstract: A method and directory system that recognizes and represents the subset of sharing patterns present in an application is provided. As used herein, the term sharing pattern refers to a group of processors accessing a single memory location in an application. The sharing pattern is decoupled from each cache line and held in a separate directory table. The sharing pattern of a cache block is the bit vector representing the processors that share the block. Multiple cache lines that have the same sharing pattern point to a common entry in the directory table. In addition, when the table capacity is exceeded, patterns that are similar to each other are dynamically collated into a single entry.
    Type: Application
    Filed: September 7, 2012
    Publication date: January 30, 2014
    Applicant: UNIVERSITY OF ROCHESTER
    Inventors: Hongzhou ZHAO, Arrvindh SHRIRAMAN, Sandhya DWARKADAS
  • Publication number: 20120179877
    Abstract: The present invention employs three decoupled hardware mechanisms: read and write signatures, which summarize per-thread access sets; per-thread conflict summary tables, which identify the threads with which conflicts have occurred; and a lazy versioning mechanism, which maintains the speculative updates in the local cache and employs a thread-private buffer (in virtual memory) only in the rare event of an overflow. The conflict summary tables allow lazy conflict management to occur locally, with no global arbitration (they also support eager management). All three mechanisms are kept software-accessible, to enable virtualization and to support transactions of arbitrary length.
    Type: Application
    Filed: March 16, 2012
    Publication date: July 12, 2012
    Applicant: University of Rochester, Office of Technology Transfer
    Inventors: Arrvindh SHRIRAMAN, Sandhya DWARKADAS, Michael SCOTT
  • Patent number: 8180971
    Abstract: In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.
    Type: Grant
    Filed: October 26, 2010
    Date of Patent: May 15, 2012
    Assignee: University of Rochester
    Inventors: Michael Scott, Sandhya Dwarkadas, Arrvindh Shriraman, Virendra Marathe, Michael F. Spear
  • Publication number: 20110099335
    Abstract: In a transactional memory technique, hardware serves simply to optimize the performance of transactions that are controlled fundamentally by software. The hardware support reduces the overhead of common TM tasks—conflict detection, validation, and data isolation—for common-case bounded transactions. Software control preserves policy flexibility and supports transactions unbounded in space and in time. The hardware includes 1) an alert-on-update mechanism for fast software-controlled conflict detection; and 2) programmable data isolation, allowing potentially conflicting readers and writers to proceed concurrently under software control.
    Type: Application
    Filed: October 26, 2010
    Publication date: April 28, 2011
    Applicant: University of Rochester
    Inventors: Michael L. Scott, Sandhya Dwarkadas, Arrvindh Shriraman, Virendra Marathe, Michael F. Spear