Abstract: Described herein are various embodiments of wafer-on-wafer manufacturing processes and devices that can be produced during or as a result of such processes. In a wafer-on-wafer process, two or more wafers including semiconductor, conductive, and/or insulating material with circuit components formed thereon can be bonded and diced to yield assemblies each including multiple dies. In some implementations, one die can include one or more integrated passive devices (e.g., deep trench capacitors) and one die can include power delivery circuitry, such as power regulation circuitry (e.g., voltage regulation circuitry).

Abstract: The disclosed semiconductor device can include a plurality of stacked circuit dies and a carrier attached to the plurality of stacked circuit dies. A plurality of redistribution layers in the carrier can provide lateral communication for one or more circuit dies of the plurality of stacked circuit dies. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed semiconductor device can include a plurality of stacked circuit dies and a mold compound introduced into a top tier of the plurality of stacked circuit dies. The disclosed semiconductor device also includes a carrier-less enclosure attached to the top tier of the plurality of stacked circuit dies. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Disclosed herein are an integrated circuit die stack and an integrated circuit die package assembly having the integrated circuit die stack. The integrated circuit die stack includes a plurality of integrated circuit dice disposed in a first tier of the die stack and a plurality of integrated circuit dice disposed in a second tier of the die stack. The plurality of integrated circuit dice of the second tier are stacked vertically above the plurality of the integrated circuit dice of the first tier and include a bridge die. The bridge die couples with at least two dice of the first tier and includes an integrated passive device coupled with a routing connection.

Abstract: Disclosed herein are a dual-sided bridge die, an integrated circuit die package assembly having the dual-sided bridge die, and a method for fabricating the integrated circuit die package assembly. A dual-sided bridge die includes a substrate; a first redistribution layer built on a top surface of the substrate and configured to couple with a bottom surface of a first integrated circuit die; and a second redistribution layer built on a bottom surface of the substrate and configured to couple with a top surface of a second integrated circuit die. The top surface and the bottom surface of the substrate are respectively disposed on opposite sides of the substrate.

Abstract: A disclosed method can include (i) forming a cavity in a substrate core for a semiconductor device from a floor of the substrate core to a ceiling of the substrate core, (ii) bonding an electronic component to an element through a bonding layer to form an electronic component aggregation, (iii) disposing the electronic component aggregation within the cavity, and (iv) filling the cavity. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.

Abstract: Disclosed herein is an integrated circuit die stack and an integrated circuit die package assembly having the integrated circuit die stack. The integrated circuit die stack includes first plurality of integrated circuit dice disposed in a first tier of the die stack, and the first plurality of integrated circuit dice include a first integrated circuit die and a bridge die. The integrated circuit die stack further includes a second plurality of integrated circuit dice disposed in a second tier of the die stack, and the second plurality of integrated circuit dice are stacked vertically above the first plurality of the integrated circuit dice of the first tier and include a second integrated circuit die and a third integrated circuit die. The bridge die couples with both the second integrated circuit die and the third integrated circuit die.

Abstract: A chip package and method for fabricating the same are provided that include a IC dies bonded to a thermal carrier having a plurality of metallic pillars. In one example, a chip package includes an interconnect routing structure and a first die disposed on a first surface of the interconnect routing structure. The first die has a circuitry connected to a circuitry of the interconnect routing structure. The chip package also includes a second die at least partially disposed over the first die. The second die has a circuitry connected to the circuitry of the first die. A thermal carrier is bonded on the second die. At least one of the thermal carrier, the first die, or the second die includes a plurality of metallic pillars configured to transfer heat, wherein the plurality of metallic pillars are electrically floating.

Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a substrate, forming a second trench capacitor within an insulating layer overlying the substrate, and connecting the first and second trench capacitors through connection vias that extend through the insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more tiers of trench capacitors.

Abstract: A method for increasing capacitance density within an integrated passive device can include forming a first trench capacitor within a first insulating layer overlying a substrate, forming a second trench capacitor within a second insulating layer overlying the first insulating layer, and connecting the first and second trench capacitors through connection vias that extend through the second insulating layer to form an integrated passive device (IPD) capacitor. A high capacitance density device can include a stacked and co-integrated architecture of two or more such layers.

Abstract: A disclosed method can include (i) positioning a first surface of a component of a semiconductor device on a first plated through-hole, (ii) covering, with a layer of dielectric material, at least a second surface of the component that is opposite the first surface of the component, (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity, and (iv) depositing conductive material in the cavity to form a second plated through-hole on the second surface of the component. Various other apparatuses, systems, and methods are also disclosed.

Abstract: A semiconductor device includes a power delivery device die stack including a plurality of vertically arranged power delivery device dies. The plurality of power delivery device dies including at least a first power delivery device die and a second power delivery device die electrically connected to the first power delivery device die. The semiconductor device includes at least one external interconnect for providing a power input to the power delivery device die stack and at least one external interconnect for supplying a power output from the power delivery device die stack.

Abstract: An electronic device includes a first integrated circuit die, a support structure, and a second integrated circuit die and may include a spacer. The support structure includes a circuit element. The support structure has a thickness of at least 110 microns. The spacer or second integrated circuit die includes a conductor. The spacer or second integrated circuit die is disposed between the first integrated circuit die and the support structure. The conductor is electrically coupled to the integrated circuit die or the circuit element of the support structure. The electronic device provides more flexibility to a designer by allowing a circuit element or circuit that occupies a significant area to be in the support structure.

Abstract: A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.

Abstract: A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.

Abstract: A system is provided for interconnecting multiple functional dies on a single substrate, including: (1) multiple global links in the substrate; (2) multiple local links in the substrate; and (3) multiple utility dies on the substrate, wherein each of the utility dies is connected to at least one of the global links, the utility dies are configured to communicate with one another through the global links, each of the utility dies is connected to at least one of the local links and is configured to communicate with at least one of the functional dies through the at least one of the local links. In some embodiments, an antenna is integrated into the substrate.

Abstract: A flexible device includes: (1) a flexible substrate; and (2) an interconnect disposed over the flexible substrate, wherein the interconnect has a varying vertical displacement along its length, relative to a top surface of the flexible substrate.

Abstract: A system is provided for interconnecting multiple functional dies on a single substrate, including: (1) multiple global links in the substrate; (2) multiple local links in the substrate; and (3) multiple utility dies on the substrate, wherein each of the utility dies is connected to at least one of the global links, the utility dies are configured to communicate with one another through the global links, each of the utility dies is connected to at least one of the local links and is configured to communicate with at least one of the functional dies through the at least one of the local links. In some embodiments, an antenna is integrated into the substrate.