Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that write data having mixed deletion characteristics sequentially to a plurality of data entries of a first physical erase block (PEB) in intermediate storage. The data having the mixed deletion characteristics includes first data having a first deletion characteristic. The processor has programmed instructions that maintain metadata in a plurality of metadata entries in a log. The metadata corresponds to the data having the mixed deletion characteristics. The processor has programmed instructions that identify, using the log, the first data having the first deletion characteristic and evacuate the first data having the first deletion characteristic to a second PEB in main memory.

Abstract: Disclosed is an apparatus including a memory system. The memory system includes a controller that assigns a first PEC to a first metablock based on a first number of structures of a memory across which the first metablock is distributed. The controller assigns a second PEC to a second metablock based on a second number of the structures of the memory across which the second metablock is distributed. The controller selects one of the first metablock or the second metablock to be used based on the first PEC and the second PEC.

Abstract: An illustrative embodiment disclosed herein is an apparatus including a processor having programmed instructions that write data having mixed deletion characteristics sequentially to a plurality of data entries of a first physical erase block (PEB) in intermediate storage. The data having the mixed deletion characteristics includes first data having a first deletion characteristic. The processor has programmed instructions that maintain metadata in a plurality of metadata entries in a log. The metadata corresponds to the data having the mixed deletion characteristics. The processor has programmed instructions that identify, using the log, the first data having the first deletion characteristic and evacuate the first data having the first deletion characteristic to a second PEB in main memory.

Abstract: The disclosure relates to optimizing a mount process at a data storage device. The storage device communicates with a host using a mount process and mounts a master table, the master table caching translation table pointers associated with a boot partition. The storage device then sends a ready signal to the host indicating that the storage device is ready to receive a boot partition read command from the host. The storage device suspends the mount process for a window of time to receive the boot partition read command and executes the boot partition read command if the boot partition read command is received during the window of time. Accordingly, by caching boot partition pointers in the master table, the mount time of the boot partition is shortened to allow the storage device to send the ready signal earlier and provide the host with earlier access to the boot partition.

Abstract: Disclosed is an apparatus including a memory system. The memory system includes a controller that assigns a first PEC to a first metablock based on a first number of structures of a memory across which the first metablock is distributed. The controller assigns a second PEC to a second metablock based on a second number of the structures of the memory across which the second metablock is distributed. The controller selects one of the first metablock or the second metablock to be used based on the first PEC and the second PEC.

Abstract: The disclosure relates to optimizing a mount process at a data storage device. The storage device communicates with a host using a mount process and mounts a master table, the master table caching translation table pointers associated with a boot partition. The storage device then sends a ready signal to the host indicating that the storage device is ready to receive a boot partition read command from the host. The storage device suspends the mount process for a window of time to receive the boot partition read command and executes the boot partition read command if the boot partition read command is received during the window of time. Accordingly, by caching boot partition pointers in the master table, the mount time of the boot partition is shortened to allow the storage device to send the ready signal earlier and provide the host with earlier access to the boot partition.

Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.

Abstract: A system on a chip or storage device has a dynamic process for handling system events that are transmitted at varying transmission rates. This dynamic process is a hybrid mode of operation that tailors the use of time stamp information according to the dynamic flow of events that are submitted in the system. Relative time stamps can be used along with explicit time stamps. Periodic wrap around events which use relative time stamps based on the periodic wrap events may be suppressed when there were no events between consecutive wrap around events. When an asynchronous event occurs during the suppression, the event is identified with a high precision time stamp (HPTS) rather than a relative time stamp. The periodic wrap around events can be re-initiated after the HPTS event is stamped.

Abstract: In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode.

Abstract: A memory system and method for securing volatile memory during sleep mode using the same ECC module used to secure non-volatile memory during active mode are provided. In one embodiment, a memory system is provided comprising a volatile memory, a non-volatile memory, and an error correction code (ECC) module. The ECC module is configured to encode, decode, and correct data stored in the volatile memory when the memory system enters and exits a sleep mode and is further configured to encode, decode, and correct data stored in the non-volatile memory when the memory system is in an active mode. Other embodiments are possible.

Abstract: Apparatuses and methods implemented therein are disclosed for generating event codes that include the source of the events that caused the generation of the event codes. In one embodiment the apparatus comprises a memory, a processor, logic element and an event generator. The memory is configured to store instructions corresponding to a scheduler and instructions corresponding to a first thread and a second thread. The processor is configured to execute instructions corresponding to the scheduler wherein the scheduler selects a one of the first or second thread wherein the processor executes instructions corresponding to the selected one of the first or second thread. The logic element is configured to receive an identifier corresponding to the selected thread and a received asynchronous event. The logic element produces a concatenated event identifier comprising the thread identifier and the received asynchronous event.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes writing an indication of a first error rate of a first set of bits to the non-volatile memory. The first set of bits is sensed from a word line of the non-volatile memory. The word line is sensed to generate a second set of bits in response to a first power-on event being initiated at the data storage device after writing the indication of the first error rate to the non-volatile memory. The method further includes setting a data retention flag in response to a difference between the first error rate and a second error rate associated with the second set of bits satisfying a threshold.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

Abstract: A data storage device includes a non-volatile memory and a controller. A method includes writing an indication of a first error rate of a first set of bits to the non-volatile memory. The first set of bits is sensed from a word line of the non-volatile memory. The word line is sensed to generate a second set of bits in response to a first power-on event being initiated at the data storage device after writing the indication of the first error rate to the non-volatile memory. The method further includes setting a data retention flag in response to a difference between the first error rate and a second error rate associated with the second set of bits satisfying a threshold.

Abstract: Apparatuses and methods implemented therein are disclosed for generating event codes and time stamped events from the generated event codes. In one embodiment the apparatus comprises a register, a counter, a timestamp fraction generator and an event code generator. The register is configured to receive a one of a set of asynchronous events. The counter is configured to receive a clock signal and generate periodic events of a configurable periodicity. The timestamp fraction generator is coupled to the register and generates a timestamp fraction in response to receiving an asynchronous event by obtaining a count from the counter at substantially the same time that the event is received. Finally, the event code generator generates an event code from the timestamp fraction and an identifier corresponding to the event.

Abstract: Apparatuses and methods implemented therein are disclosed for generating event codes that include the source of the events that caused the generation of the event codes. In one embodiment the apparatus comprises a memory, a processor, logic element and an event generator. The memory is configured to store instructions corresponding to a scheduler and instructions corresponding to a first thread and a second thread. The processor is configured to execute instructions corresponding to the scheduler wherein the scheduler selects a one of the first or second thread wherein the processor executes instructions corresponding to the selected one of the first or second thread. The logic element is configured to receive an identifier corresponding to the selected thread and a received asynchronous event. The logic element produces a concatenated event identifier comprising the thread identifier and the received asynchronous event.

Abstract: A data storage device includes a controller and a non-volatile memory that includes a three-dimensional (3D) memory. A method includes initiating a write operation to write first data to a first word line of a multi-level cell (MLC) block of the non-volatile memory. The method further includes compensating, in response to an event that interrupts programming at the first word line, for incompletion of a write disturb effect at the MLC block due to the event by copying second data from a second word line of the MLC block to a second block of the non-volatile memory or by writing dummy data to the second word line.

Abstract: A method for data integrity protection includes receiving items of data for storage in a storage medium. The items are grouped into multiple groups, such that at least some of the groups include respective pluralities of the items. A respective group signature is computed over each of the groups, thereby generating multiple group signatures. An upper-level signature is computed over the group signatures. Groups of the items, the group signatures, and the upper-level signature are stored in respective locations in the storage medium.

Abstract: Side channel attacks against a computing device are prevented by combinations of scrambling data to be stored in memory and scrambling the memory addresses of the data using software routines to execute scrambling and descrambling functions. Encrypted versions of variables, data and lookup tables, commonly employed in cryptographic algorithms, are thus dispersed into pseudorandom locations. Data and cryptographic primitives that require data-dependent memory accesses are thus shielded from attacks that could reveal memory access patterns and compromise cryptographic keys.