Abstract: A first-in first-out (FIFO) memory interface is provided by coupling an input register and an output register to a conventional static random access memory (SRAM). The registers and SRAM are coupled to control logic that controls the timing of shift-in (write) and shift-out (read) operations. Upon receipt of a write request signal, input data is received from the requesting device and buffered within the input register. The buffered data is then stored in the SRAM during a write operation. Upon receipt of a read request signal, the data previously buffered in the output register is provided to the requesting device and during an associated read operation the next stored data in the SRAM is retrieved and buffered within the output register. The control logic is programmable and is therefore capable of supporting different SRAM configurations. The control logic can also be implemented in a conventional programmable logic device.