Patents by Inventor Arshad Rahman
Arshad Rahman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948534Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.Type: GrantFiled: July 29, 2022Date of Patent: April 2, 2024Assignee: ATI Technologies ULCInventors: Jun Lei, Syed Athar Hussain, David I. J. Glen, Rajeevan Panchacharamoorthy, Fatemeh Amirnavaei, David Galiffi, Arshad Rahman, Boris Ivanovic
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Patent number: 11699408Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.Type: GrantFiled: December 22, 2020Date of Patent: July 11, 2023Assignee: ATI Technologies ULCInventors: Arshad Rahman, Rajeevan Panchacharamoorthy, Boris Ivanovic
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Publication number: 20230118079Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.Type: ApplicationFiled: July 29, 2022Publication date: April 20, 2023Inventors: Jun LEI, Syed Athar HUSSAIN, David I.J. GLEN, Rajeevan PANCHACHARAMOORTHY, Fatemeh AMIRNAVAEI, David GALIFFI, Arshad RAHMAN, Boris IVANOVIC
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Patent number: 11430410Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.Type: GrantFiled: June 1, 2020Date of Patent: August 30, 2022Assignee: ATI TECHNOLOGIES ULCInventors: Jun Lei, Syed Athar Hussain, David I. J. Glen, Rajeevan Panchacharamoorthy, Fatemeh Amirnavaei, David Galiffi, Arshad Rahman, Boris Ivanovic
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Publication number: 20220199047Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.Type: ApplicationFiled: December 22, 2020Publication date: June 23, 2022Inventors: Arshad Rahman, Rajeevan Panchacharamoorthy, Boris Ivanovic
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Patent number: 11276135Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.Type: GrantFiled: April 23, 2020Date of Patent: March 15, 2022Assignee: ATI Technologies ULCInventors: Syed Arshad Rahman, Michael I. Hvizdos, Leonid Shamis
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Publication number: 20210375234Abstract: A display system modifies display cycles of one or more displays to perform a system operation while avoiding visual perturbations at the one or more displays. The display system modifies, synchronizes, or both, blanking periods of the one or more displays such that blanking periods equal or exceed a blackout duration and overlap for at least the blackout duration. Then the system performs the system operation during an overlapping portion of the one or more blanking periods, where the system operation reduces availability of display data at the one or more displays.Type: ApplicationFiled: June 1, 2020Publication date: December 2, 2021Inventors: Jun LEI, Syed Athar HUSSAIN, David I.J. GLEN, Rajeevan PANCHACHARAMOORTHY, Fatemeh AMIRNAVAEI, David GALIFFI, Arshad RAHMAN, Boris IVANOVIC
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Publication number: 20200258187Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.Type: ApplicationFiled: April 23, 2020Publication date: August 13, 2020Applicant: ATI Technologies ULCInventors: Syed Arshad Rahman, Michael I. Hvizdos, Leonid Shamis
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Patent number: 10672095Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.Type: GrantFiled: December 15, 2017Date of Patent: June 2, 2020Assignee: ATI TECHNOLOGIES ULCInventors: Syed Arshad Rahman, Michael I. Hvizdos, Leonid Shamis
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Publication number: 20190188822Abstract: Techniques for improving data transfer in a system having multiple accelerated processing devices (“APDs”) are described herein. In such a system, multiple APDs are coupled to a processor (e.g., a central processing unit (“CPU”)) via a general interconnect fabric and to each other via a high speed interconnect. The techniques herein increase the effective bandwidth for transfer of data between the CPU and the APD by transmitting data to both APDs through the portion of the interconnect fabric coupled to each respective APD. Then, one of the APDs transfers data to the other APD or to the processor via the high speed inter-APD interconnect. Although data transferred “indirectly” through the helper APD takes slightly more time to be transferred than a direct transfer, the total effective bandwidth to the target is increased due to the high-speed inter-APD interconnect.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Applicant: ATI Technologies ULCInventors: Syed Arshad Rahman, Michael I. Hvizdos, Leonid Shamis
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Patent number: 10002028Abstract: A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating.Type: GrantFiled: July 31, 2015Date of Patent: June 19, 2018Assignee: ATI Technologies ULCInventors: Joseph Andonieh, Arshad Rahman
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Publication number: 20150339171Abstract: A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating.Type: ApplicationFiled: July 31, 2015Publication date: November 26, 2015Applicant: ATI TECHNOLOGIES ULCInventors: Joseph Andonieh, Arshad Rahman
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Patent number: 8797332Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.Type: GrantFiled: December 14, 2011Date of Patent: August 5, 2014Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Paul Blinzer, Leendert Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Woller, Arshad Rahman
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Patent number: 8675002Abstract: A method for providing two or more processors access to a single command buffer is provided. The method includes receiving instructions in the command buffer from a central processor, at least one of the instructions being designated for a particular one of the two or more processors. The method also includes sending the at least one instruction to only the particular processor.Type: GrantFiled: June 9, 2010Date of Patent: March 18, 2014Assignee: ATI Technologies, ULCInventors: Joseph Andonieh, Arshad Rahman
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Patent number: 8578129Abstract: In a CPU, the CPU having multiple CPU cores, each core having a first machine specific register, a second machine specific register, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address contained in the second machine specific register, wherein the physical address is able to receive writes that affect IOMMUv2 page table invalidations.Type: GrantFiled: December 14, 2011Date of Patent: November 5, 2013Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Paul Blinzer, Leendert Peter Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Roy Woller, Arshad Rahman
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Publication number: 20130159664Abstract: In a CPU of the combined CPU/APD architecture system, the CPU having multiple CPU cores, each core having a first machine specific register for receiving a physical page table/page directory base address, a second machine specific register for receiving a physical address pointing to a location controlled by an IOMMUv2 that is communicatively coupled to an APD, and microcode which when executed causes a write notification to be issued to the physical address contained in the second machine specific register; receiving in the first machine specific register of a CPU core, a physical page table/page directory base address, receiving in the second machine specific register of the CPU core, a physical address pointing to a location controlled by the IOMMUv2, determining that a control register of the CPU core has been updated, and responsive to the determination that the control register has been updated, executing microcode in the CPU core that causes a write notification to be issued to the physical address conType: ApplicationFiled: December 14, 2011Publication date: June 20, 2013Inventors: Paul BLINZER, Leendert Peter Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Roy Woller, Arshad Rahman
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Publication number: 20120162234Abstract: Methods and apparatus are provided, as an aspect of a combined CPU/APD architecture system, for discovering and reporting properties of devices and system topology that are relevant to efficiently scheduling and distributing computational tasks to the various computational resources of a combined CPU/APD architecture system. The combined CPU/APD architecture unifies CPUs and APDs in a flexible computing environment. In some embodiments, the combined CPU/APD architecture capabilities are implemented in a single integrated circuit, elements of which can include one or more CPU cores and one or more APD cores. The combined CPU/APD architecture creates a foundation upon which existing and new programming frameworks, languages, and tools can be constructed.Type: ApplicationFiled: December 14, 2011Publication date: June 28, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Paul Blinzer, Leendert Van Doorn, Gongxian Jeffrey Cheng, Elene Terry, Thomas Woller, Arshad Rahman
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Publication number: 20120001905Abstract: A computer based rendering system is provided. The computer based rendering system includes an abstraction mechanism to provide configuring instructions to two or more processors, the configuring instructions being operative to facilitate scene rendering. The configuring provides processor setup instructions to at least one driver. Each of the two or more processors renders a respective portion of the scene independent of the other of the processors.Type: ApplicationFiled: June 30, 2011Publication date: January 5, 2012Applicant: ATI Technologies, ULCInventors: Joseph ANDONIEH, Arshad Rahman
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Publication number: 20120001925Abstract: A method for rendering a scene across N number of processors is provided. The method includes evaluating performance statistics for each of the processors and establishing load rendering boundaries for each of the processors, the boundaries defining a respective portion of the scene. The method also includes dynamically adjusting the boundaries based upon the establishing and the evaluating.Type: ApplicationFiled: June 30, 2011Publication date: January 5, 2012Applicant: ATI Technologies, ULCInventors: Joseph ANDONIEH, Arshad RAHMAN
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Patent number: 5901310Abstract: Initializing and configuring computer hardware with firmware stored in compressed form in nonvolatile semiconductor memory. Upon startup of the computer hardware, decompression software decompress the firmware, which is then stored in another memory. The computer hardware may be an adapter board (e.g., a graphics board connected to PCI bus), the nonvolatile semiconductor memory may be physically located on the adapter board, and the firmware may be firmware for initializing and configuring the adapter board. The decompression software may be stored in the same nonvolatile semiconductor memory as the firmware, and may be written in a machine-independent language (e.g., a Forth-based language). The compression technique used may include both run-length encoding and pattern compression, and may operate at the bit level.Type: GrantFiled: September 11, 1997Date of Patent: May 4, 1999Assignee: ATI Technologies, Inc.Inventors: Arshad Rahman, Vladimir Velenta, Anthony Scarpino