Abstract: An integrated circuit in which the address and data inputs for a clock register to program a clock is also used for device ID and revision number. A shadow register is provided which is accessible to output the ID and revision number when (1) the regular clock register is addressed, and (2) a particular data input for activating the shadow register appears on the data input to the clock register.

Abstract: A single, standard general purpose register address accesses not only the general purpose register, but, pursuant to user programming, FIFO counter status. In one embodiment, either the receive or transmit FIFO counter status can be accessed. The use of the general purpose register address for this purpose is preferably programmed using a bit from the control register on the chip.

Abstract: A UART compatible to a prior art UART provides a baud rate generator which can accept a higher frequency crystal oscillator to generate baud rates compatible with baud rates generated by the prior art UART without increasing the size of the frequency division circuit. In one embodiment, the UART of the present invention provides the capability for programmable flow control, including flow control for binary file transfers, using user-programmable multiple-character flow control words. In one embodiment, a sleep mode allows power conservation in the UART of the present invention.