Patents by Inventor Artashes R. Nazarian

Artashes R. Nazarian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated injection circuit
    Patent number: 4243895
    Abstract: An integrated injection circuit is proposed which comprises a current generator and a normally cutoff n-channel field-effect transistor. The gate of the FET is connected to the current generator and to the input electrode of the circuit, the source is grounded and the drain is connected to the output electrode of the circuit. The gate of the FET is designed as at least one non-injecting rectifying contact.
    Type: Grant
    Filed: January 4, 1978
    Date of Patent: January 6, 1981
    Inventors: Artashes R. Nazarian, Vyacheslav Y. Kremlev, Vilyam N. Kokin, Viktor I. Sladkov, Boris V. Venkov, Vadim V. Lavrov
  • Integrated logic circuit with a current source made as a field-effect transistor
    Patent number: 4175240
    Abstract: The integrated logic circuit of the invention comprises a switching field-effect transistor and a current source, which is another field-effect transistor having its conductivity complementary to that of the switching field-effect transistor. The second field-effect transistor has its gate coupled to the source of the switching field-effect transistor, and to an electrode of a power supply its source coupled to the other power supply circuit electrode and its drain coupled to the gate of the switching field-effect transistor. The gate and the drain of the switching field-effect transistor are respectively connected to the input and the output of the circuit.
    Type: Grant
    Filed: January 3, 1978
    Date of Patent: November 20, 1979
    Inventors: Vyacheslav Y. Kremlev, Artashes R. Nazarian, Alexei V. Lubashevsky, Vilyam N. Kokin
  • Integrated logic circuit
    Patent number: 4160918
    Abstract: An integrated injection logic circuit comprises a switching element using a unipolar FET whose gates are connected to the collectors of a load transistor. The emitter of the load transistor is connected to a power supply and the base area is combined with the source of the unipolar FET and grounded. Connected to the gates of the unipolar FET and to the base area of the load transistor are double-pole gating elements. The number of such elements is equal to the number of gates of the unipolar FET. The conduction voltage of the gating elements is lower than that across the p-n junctions of the respective gates of the unipolar FET.
    Type: Grant
    Filed: December 29, 1977
    Date of Patent: July 10, 1979
    Inventors: Artashes R. Nazarian, Vyacheslav Y. Kremlev, Vilyam N. Kokin, Nikolai M. Manzha