Abstract: Frameworks and methods for executing large-scale build and operate programs, such as sporting events, and particularly an Olympic Games. A framework of interlinked build, operate, and management processes is formed in accordance with the program requirements, which are specified in terms of deliverable products or service levels. Links between individual processes can only be traversed when exit criteria are satisfied. Methodologies are described that can be used to determine the exit criteria. Once a framework is established, a schedule control plan, by way of significant milestones, is determined. The milestones are chosen to correspond with links between processes that span process streams or project teams.

Abstract: A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: A design structure for repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

Abstract: There is provided a decoupled fetch-execute engine with static branch prediction support. A method for prefetching targets of branch instructions in a computer processing system having instruction fetch decoupled from an execution pipeline includes the step of generating a prepare-to-branch (PBR) operation. The PBR operation includes address bits corresponding to a branch paired thereto and address bits corresponding to an expected target of the branch. The execution of the PBR operation is scheduled prior to execution of the paired branch to enforce a desired latency therebetween. Upon execution of the PBR operation, it is determined whether the paired branch is available using the address bits of the PBR operation corresponding to the paired branch. When the paired branch is available, the expected branch target is fetched using the address bits of the PBR operation corresponding to the expected branch target.

Abstract: The present invention relates to novel plasmid constructs useful for the delivery of DNA vaccines. The present invention provides novel plasmids having a transcription cassette capable of directing the expression of a vaccine nucleic acid insert encoding immunogens derived from any pathogen, including fungi, bacteria and viruses. The present invention, however, is particularly useful for inducing in a patient an immune response against pathogenic viruses such as HIV, measles or influenza. Immunodeficiency virus vaccine inserts of the present invention express non-infectious HIV virus-like particles (VLP) bearing multiple viral epitopes. VLPs allow presentation of the epitopes to multiple histocompatability types, thereby reducing the possibility of the targeted virus escaping the immune response. Also described are methods for immunizing a patient by delivery of a novel plasmid of the present invention to the patient for expression of the vaccine insert therein.

Abstract: An efficient, cost effective eccentric bearing assembly is provided for use in a multiple piston hydraulic pump. The eccentric bearing assembly includes a roller bearing having an annular race. The race includes a groove around its outside perimeter. The groove engagably receives parti-spherical faces of a pair of opposed pistons. The parti-spherical face evenly loads the race and rollers as the race reciprocates with the eccentric. The invention avoids the use of rotating thrust bearings and instead axially supports the piston clip with stationary surfaces. Placement of the parti-spherical face or an optional conical face, at the interface between the pistons and the grooved race maintains the sliding contact point for piston intake strokes near the center of the face.

Abstract: A composite polymeric material having metallic surface properties is prepared by subliming solid crystalline polymeric sulfur nitride to a vapor, and thereafter condensing the polymeric sulfur nitride vapor onto the surface of a highly-oriented thermoplastic polymeric substrate to thereby form on the substrate an epitaxial crystalline polymeric sulfur nitride film. The polymeric sulfur nitride film is completely oriented parallel to the direction of orientation of the substrate and has a relatively high degree of anisotropy with respect to its electrical conductivity and optical properties.