Abstract: A performance enhanced simulation modeling technique is provided for optimizing integrated circuit layout. The modeling technique utilizes a performance enhanced methodology. Namely, a physical design enhances performance design to ensure that the simulation model takes into account placement and interconnect when determining whether or not the resulting integrated circuit will operate properly at required speed with actual load being applied. An initial sizing of selected devices within a network is performed using estimated time duration and load factors. Subsequently, select devices are resized according to more optimal physical time duration and load. The entire simulation modeling is achieved using computer program simulation prior to the generation of a final layout placeable upon a silicon substrate. As such, simulation methodology provides a flow to correct unexpected performance errors resulting from physical design.

Abstract: In a watchdog timer, the selected codes identifying the format of a watchdog timer algorithm, such as the intervals within which a watchdog timer status must be issued by the host processor, are supplied as hardwired preset codes in programmable fuse or read only memory cells that are adapted to be programmed, but are immune from ESD, power glitches and errant software. A programmable code indicating a programmable time interval is also stored in a register protected from errant software when the watchdog timer is enabled. A selector receives the preset code and the programmable code and selects an output code indicating the time interval within which the watchdog timer must be reset by a processor status signal. The selector can be programmed to select only the preset code by supplying a selector control signal through an element that is immune from electrostatic discharge, power glitches and errant software. Also, a code fixing the watchdog timer in an on state can be supplied with ESD-immune cells.

Abstract: A random access memory cell of complementary field effect transistors that include a bit storage latch for storing binary bit information connected to a word address line and a data address line. The data address line provides bit information to the latch. This bit data is stored in the latch when the word address line is active. A switching circuit is connected to the latch that enables new data to be stored in the latch by removing the previously stored data during the time that the new data is being stored.

Abstract: An oscillator circuit including a Schmidt trigger that receives an input signal and is connected to a compensating circuit to adjust the trigger points of the Schmidt trigger. The ouput of the Schmidt trigger is connected to a push-pull driver which provides the oscillator output. The oscillator output is fed back through an external resistor and capacitor and input of the Schmidt trigger.

Abstract: A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability. Incorporation of a switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic to be turned off while power is maintained on the internal static RAM, on the digit latches, and on the R-lines which connect to both the internal and external RAM. Thus, semi-non-volatile memory (constant memory) capability may be achieved with a low standby current.