Patents by Inventor Arthur Brian LAUGHTON
Arthur Brian LAUGHTON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12242399Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.Type: GrantFiled: February 23, 2022Date of Patent: March 4, 2025Assignee: Arm LimitedInventors: Jacob Joseph, Tessil Thomas, Arthur Brian Laughton, Anitha Kona, Jamshed Jalal
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Patent number: 11860811Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.Type: GrantFiled: March 23, 2022Date of Patent: January 2, 2024Assignee: Arm LimitedInventors: Arthur Brian Laughton, Tessil Thomas, Jacob Joseph
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Patent number: 11803506Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.Type: GrantFiled: October 28, 2021Date of Patent: October 31, 2023Assignee: Arm LimitedInventors: Tessil Thomas, Anitha Kona, Jacob Joseph, Arthur Brian Laughton, Nandakishore Sastry
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Publication number: 20230305985Abstract: The present disclosure provides a system and methods for transferring data across an interconnect. One method includes, at a request node, receiving, from a source high speed serial controller, a write request from a source, dividing the write request into sequences of smaller write requests each having a last identifier, and sending, to a home node, the sequences of smaller write requests; and, at the home node, sending, to a destination high speed serial controller, the sequences of smaller write requests for assembly into intermediate write requests that are transmitted to a destination. Each sequence of smaller write requests is assembled into an intermediate write request based on the last identifier.Type: ApplicationFiled: March 23, 2022Publication date: September 28, 2023Applicant: Arm LimitedInventors: Arthur Brian Laughton, Tessil Thomas, Jacob Joseph
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Publication number: 20230267081Abstract: Peripheral components, data processing systems and methods of operating such peripheral components and data processing systems are disclosed. The systems comprise an interconnect comprising a system cache, a peripheral component coupled to the interconnect, and a memory coupled to the interconnect. The peripheral component has a memory access request queue for queuing memory access requests in a receipt order. Memory access requests are issued to the interconnect in the receipt order. A memory read request is not issued to the interconnect until a completion response for all older memory write requests has been received from the interconnect. The peripheral component is responsive to receipt of a memory read request to issue a memory read prefetch request comprising a physical address to the interconnect and the interconnect is responsive to the memory read prefetch request to cause data associated with the physical address in the memory to be cached in the system cache.Type: ApplicationFiled: February 23, 2022Publication date: August 24, 2023Inventors: Jacob JOSEPH, Tessil THOMAS, Arthur Brian LAUGHTON, Anitha KONA, Jamshed JALAL
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Patent number: 11720511Abstract: An apparatus comprises interface circuitry to receive requests and selection circuitry responsive to the interface circuitry receiving a given request to select, from a pool of items, at least one selected item to be associated with the given request. The selection circuitry comprises a plurality of nodes arranged in a tree structure, each node being configured to select m output signals from n input signals provided to that node, wherein n>m. The apparatus comprises control circuitry configured to output, in dependence on a type of the given request, a suppression signal, and the tree structure comprises a gate node configured to suppress, in response to the suppression signal having a first value, selection from input signals received from a given portion of the tree structure to prevent a subset of the pool of items from being selected for at least one type of request.Type: GrantFiled: June 2, 2021Date of Patent: August 8, 2023Assignee: Arm LimitedInventor: Arthur Brian Laughton
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Publication number: 20230140069Abstract: A data processing apparatus is provided that includes communication circuitry to transmit an interconnect message to a root port using a physical address mapped to the root port. Translation circuitry encapsulates, within the interconnect message to the root port, a Peripheral Component Interconnect Express (PCIe) message to a destination, the PCIe message having routing information encoded as a PCIe bus number associated with the destination.Type: ApplicationFiled: October 28, 2021Publication date: May 4, 2023Inventors: Tessil THOMAS, Anitha KONA, Jacob JOSEPH, Arthur Brian LAUGHTON, Nandakishore SASTRY
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Publication number: 20220391342Abstract: An apparatus comprises interface circuitry to receive requests and selection circuitry responsive to the interface circuitry receiving a given request to select, from a pool of items, at least one selected item to be associated with the given request. The selection circuitry comprises a plurality of nodes arranged in a tree structure, each node being configured to select m output signals from n input signals provided to that node, wherein n>m. The apparatus comprises control circuitry configured to output, in dependence on a type of the given request, a suppression signal, and the tree structure comprises a gate node configured to suppress, in response to the suppression signal having a first value, selection from input signals received from a given portion of the tree structure to prevent a subset of the pool of items from being selected for at least one type of request.Type: ApplicationFiled: June 2, 2021Publication date: December 8, 2022Inventor: Arthur Brian Laughton
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Patent number: 10810146Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.Type: GrantFiled: November 26, 2018Date of Patent: October 20, 2020Assignee: ARM LIMITEDInventors: Arthur Brian Laughton, Chiranjeev Acharya, Eduard Vardanyan
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Patent number: 10796040Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second rType: GrantFiled: February 5, 2019Date of Patent: October 6, 2020Assignee: ARM LIMITEDInventors: Sean James Salisbury, Zheng Xu, Arthur Brian Laughton, Charles Filip Brej
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Patent number: 10740032Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.Type: GrantFiled: October 1, 2018Date of Patent: August 11, 2020Assignee: Arm LimitedInventors: Chiranjeev Acharya, Sean James Salisbury, Eduard Vardanyan, Arthur Brian Laughton
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Publication number: 20200250281Abstract: A method comprises generating, using a computer, an integrated circuit layout including a plurality of data handling nodes interconnected by routing circuitry defining data packet routes between the plurality of data handling nodes; for a transaction source node configured to generate data packets associated with a data handling translation between that transaction source node and a transaction target node and having one or more routing data fields controlling routing of the data packet, detecting, using the computer, a difference between a first routing controlled by the one or more routing data fields and a selected second routing provided by the integrated circuit layout; and providing, using the computer, one or more data mapping nodes in the integrated circuit layout to map an initial value of one or more of the routing data fields of a data packet generated by the transaction source node to a mapped data value, so that the mapped data value controls routing of the data packet using the selected second rType: ApplicationFiled: February 5, 2019Publication date: August 6, 2020Inventors: Sean James SALISBURY, Zheng XU, Arthur Brian LAUGHTON, Charles Filip BREJ
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Patent number: 10437750Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.Type: GrantFiled: December 21, 2017Date of Patent: October 8, 2019Assignee: ARM LimitedInventors: Arthur Brian Laughton, Sean James Salisbury, Chiranjeev Acharya, Eduard Vardanyan
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Patent number: 10423346Abstract: An apparatus for processing data 2 contains multiple power domains which may be in a non-retaining power state or a retaining power state. If a power domain is in a non-retaining power state in which it is not able to retain a copy of a stored parameter value and it is switched into a retaining power state in which it requires a copy of that parameter value, then it fetches the parameter value from a store within another power domain. One of the power domains contains a master copy of the parameter value to which writes changing in the parameter value are made. At least one of the other power domains fetches a copy of the parameter value if required from a power domain other than the power domain containing the master copy.Type: GrantFiled: February 13, 2017Date of Patent: September 24, 2019Assignee: ARM LimitedInventor: Arthur Brian Laughton
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Publication number: 20190196990Abstract: An interconnect for providing data access between nodes of an integrated circuit, comprises a predetermined type of ingress port comprising routing circuitry responsive to a read-triggering request received from a requesting node to select from a selected egress port via which signals are to be routed to a destination node to control the destination node to return at least one read response dependent on data read from a target storage location. In response to the read-triggering request, the routing circuitry obtains a relative data width indication specifying whether read responses received at the selected egress port have a narrower data width than read responses to be provided to the requesting node by the predetermined type of ingress port, and controls allocation of resource for handling the read-triggering request or the at least one read response depending on the relative data width indication.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Arthur Brian LAUGHTON, Sean James SALISBURY, Chiranjeev ACHARYA, Eduard VARDANYAN
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Publication number: 20190179783Abstract: Routing circuitry 400 is provided for routing transaction requests to a selected destination node. The routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Request regulators 401, 402, 403 are provided to monitor resource usage for read, atomic and write requests, and issue circuitry 431 controls the issuing of a transaction request received from a requesting node, in dependence on resource usage monitoring performed by the request regulators. The issue circuitry controls the issuing of atomic requests in dependence on the resource usage monitored by the write request regulator and the resource usage monitored by the atomic request regulator.Type: ApplicationFiled: November 26, 2018Publication date: June 13, 2019Inventors: Arthur Brian LAUGHTON, Chiranjeev ACHARYA, Eduard VARDANYAN
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Publication number: 20190163400Abstract: Data access routing circuitry 4, 6 is provided for routing data access request to a selected destination node. The data access routing circuitry supports read requests requiring a read response, write requests requiring a write response and at least one type of atomic data access request requiring both a read response and a write response. Resource allocation circuitry 70, 71 is provided to control allocation of resource for handling data access requests which require a read response. The resource allocation circuitry 70, 71 reserves resource for handling the at least one type of atomic data access request and prevents use of the reserved resource 76 for handling read requests.Type: ApplicationFiled: October 1, 2018Publication date: May 30, 2019Inventors: Chiranjeev ACHARYA, Sean James SALISBURY, Eduard VARDANYAN, Arthur Brian LAUGHTON
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Patent number: 10255103Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.Type: GrantFiled: April 4, 2017Date of Patent: April 9, 2019Assignee: ARM LimitedInventors: Chiranjeev Acharya, Arthur Brian Laughton, Sean James Salisbury
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Publication number: 20180285145Abstract: Transaction handling apparatus comprises a response buffer; and tracking circuitry to store data defining each transaction issued by one or more transaction master devices and to control routing of a transaction response to a given transaction either to the response buffer or as an output to the transaction master device which issued the given transaction; the response buffer being configured to access an indicator for each buffered transaction response indicating whether a response has been output by the apparatus for a previously issued transaction, on which that buffered transaction response depends, and to output the buffered transaction response to the transaction master device which issued that transaction when the previously issued transaction has already been output by the apparatus.Type: ApplicationFiled: April 4, 2017Publication date: October 4, 2018Inventors: Chiranjeev ACHARYA, Arthur Brian LAUGHTON, Sean James SALISBURY
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Publication number: 20180232168Abstract: An apparatus for processing data 2 contains multiple power domains which may be in a non-retaining power state or a retaining power state. If a power domain is in a non-retaining power state in which it is not able to retain a copy of a stored parameter value and it is switched into a retaining power state in which it requires a copy of that parameter value, then it fetches the parameter value from a store within another power domain. One of the power domains contains a master copy of the parameter value to which writes changing in the parameter value are made. At least one of the other power domains fetches a copy of the parameter value if required from a power domain other than the power domain containing the master copy.Type: ApplicationFiled: February 13, 2017Publication date: August 16, 2018Inventor: Arthur Brian LAUGHTON