Abstract: A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes.

Abstract: An apparatus for automatically selecting the one of a plurality of main storage units containing a range of addresses which includes the address of the data to be accessed. The storage capacity of each storage unit is simultaneously compared with a portion of the memory address indicative of the data to be accessed to determine whether the memory address is greater than, less than or equal to the storage capacity of any memory storage unit. If the memory address is greater than the capacity of a given memory storage unit but less than or equal to the storage capacity of the next adjacent memory storage unit, that unit is automatically selected for response to the full memory address.