Abstract: A deadlock-avoidance system for a computer. In a multi-bus, multi-processor computer, one processor may request a lock on a bus, to execute a locked cycle, thereby blocking all other processors, and other agents, from access to the bus. In addition, a conflicting agent may, in effect, lock a resource which is needed by the processor to complete the cycle for which the lock was requested. These two locks can create a deadlock situation which stalls the computer: the processor and the conflicting agent have each locked a resource needed by the other. Under the invention, when a locked cycle is requested by a processor, all other operations are suspended in the computer. Then queues standing in memory controllers are emptied. If a process requested by an agent occupies a resource, such as a bridge, required by the requested locked cycle, that resource is freed. Then the locked cycle is executed.

Abstract: A multiprocessor computing apparatus that includes a mechanism for favoring at least one processor over another processor to achieve more equitable access to cached data. Logic for detecting when, for example, a remote and a local processor are attempting to access data from the cache of another local processor is disclosed. Logic that provides an advantage to the remote processor in a manner that achieves fairer access among the various processors is also disclosed.

Abstract: A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

Abstract: A cache controller for a cache memory having a number of cache lines includes a page index monitor and a page index tracker coupled to the page index monitor. The page index monitor is configured to update a thrashing value associated with a cache line identified by a first page index. The page index includes a tracking controller and a replacement tracking store. The tracking controller is configured to store a first tag and a second tag in the replacement tracking store when a first data stored in the cache line is replaced with a second data where the first data is also stored in a first main memory location identified by a first address having said first page index and said first tag, and the second data is stored in a second main memory location identified by a second address having the first page index and the second tag.

Abstract: Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Abstract: Process migration is controlled in multiple processor system by a circuit providing a rapid lookup to see if an available process has any affinity for the top N entries on the system run queue. If the currently available processor has an affinity for, i.e. has one or more lines of operands and/or instructions stored in its local cache related to the process, then the processor selects the process it has affinity for from the top N processes on the run queue. In this manner, unnecessary replacements of cache lines with data from main memory is reduced.

Abstract: A single chip cache address comparator with an on-chip static RAM for storing and checking the cache tags of an external cache memory. This cache address comparator has a built-in incrementing counter which controls the burst fill of the internal cache of a 68020/68030 microprocessor from the associated external cache memory within the required five processor clock cycles. Further, additional on-chip control logic is provided to control the 68020/68030 system buses to coordinate a burst fill operation.

Abstract: Arbitration as provided in two separate levels, first between two signals that may contend for access to a system resource, such as a memory, and second between the winner of the first arbitration and another source, such as a refresh signal timer, that must have access to the system resource periodically and independently of requests for access from the other signals. The winning signal of the first arbitration is not continuous but is divided into intervals, and the refresh timer gains control of the second arbitration at the end of each interval of control by the winning signal from the first arbitration.

Abstract: A memory addressing system includes an addressable memory provided with error checking and correction (ECC) circuits which include output latches adapted to latch corrected data read from the memory. An applied memory address is compared in a comparator with a previous memory address stored in an address latch and if a match is detected, a match signal is effective to inhibit the occurrence of the next memory cycle and to activate a decoder coupled to the output of the ECC circuits to cause transfer to the system bus of selected data from the ECC latches. If no match is detected, a memory cycle is initiated to access the desired data in the memory. A high-speed memory operation is thus achieved utilizing simple circuitry.