Patents by Inventor Arthur Fox
Arthur Fox has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240135271Abstract: Systems and methods to generate predicted variances of an operation based on data from one or more connected databases.Type: ApplicationFiled: December 11, 2023Publication date: April 25, 2024Applicant: American Airlines, Inc.Inventors: James Fox, Randeep Ramamurthy, Julianne Anderson, Arthur Busse, Marcial Lapp, Daniel Muzich, Thomas Trenga
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Publication number: 20240133867Abstract: A breath capture and analysis system includes a breath inlet for capturing a user's breath. The breath is drawn into the system and retained for analysis. The system includes a membrane that allows volatile organic compounds contained in the breath to pass therethrough. The volatile organic compounds pass into a vacuum chamber that includes a residual gas analyzer that is configured to analyze the volatile organic compounds. The analyzed breath is then vacated from the system.Type: ApplicationFiled: February 2, 2022Publication date: April 25, 2024Inventors: David Staack, Daniel Arthur McAdams, II, Matthew Leonard Burnette, Devesh Bhasin, Xin Tang, Maulik Kotecha, Kavita Rathore, Christopher Campbell, Jason G. Fox, Paul Michael Aarseth
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Publication number: 20240135270Abstract: Systems and methods to generate predicted variances of an operation based on data from one or more connected databases.Type: ApplicationFiled: December 11, 2023Publication date: April 25, 2024Applicant: American Airlines, Inc.Inventors: James Fox, Randeep Ramamurthy, Julianne Anderson, Arthur Busse, Marcial Lapp, Daniel Muzich, Thomas Trenga
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Publication number: 20240095527Abstract: Systems and techniques are described related to training one or more machine learning models for use in control of a robot. In at least one embodiment, one or more machine learning models are trained based at least on simulations of the robot and renderings of such simulations—which may be performed using one or more ray tracing algorithms, operations, or techniques.Type: ApplicationFiled: August 10, 2023Publication date: March 21, 2024Inventors: Ankur HANDA, Gavriel STATE, Arthur David ALLSHIRE, Dieter FOX, Jean-Francois Victor LAFLECHE, Jingzhou LIU, Viktor MAKOVIICHUK, Yashraj Shyam NARANG, Aleksei Vladimirovich PETRENKO, Ritvik SINGH, Balakumar SUNDARALINGAM, Karl VAN WYK, Alexander ZHURKEVICH
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Patent number: 11680927Abstract: The present invention provides a way to increase the density of Hall effect sensors on a MFL inline inspection tool mounting the sensors on a first circuit board which overlies a second circuit board. Op amps for the sensors which condition and filter the analog signal from the sensors are mounted on the first circuit board. Microprocessors mounted on the second circuit board receive the analog signal from the op amp and translate it into a digital signal. Use of the stacked circuit boards doubles the amount of area to mount the sensors and their op amps and microprocessors while maintaining the same footprint. This results in being able to increase the number of Hall effect sensors in that footprint area. In other embodiments the number of layers of circuit boards may be increased beyond two.Type: GrantFiled: March 12, 2021Date of Patent: June 20, 2023Assignee: Cypress In-Line Inspection, LLCInventors: Arthur Fox, Calvin L. Simmons, Michael P. Sheffield, William Geoffrey Callahan
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Patent number: 8468323Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly.Type: GrantFiled: March 21, 2011Date of Patent: June 18, 2013Assignee: ARRAY Portfolio LLCInventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Patent number: 8120938Abstract: A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.Type: GrantFiled: April 18, 2008Date of Patent: February 21, 2012Assignee: VNS Portfolio LLCInventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Publication number: 20110179251Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a micro-loop (100) which is capable of performing a series of operations repeatedly.Type: ApplicationFiled: March 21, 2011Publication date: July 21, 2011Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Patent number: 7966481Abstract: A microprocessor system in which an array of processors communicates more efficiently through the use of a worker mode function. Processors that are not currently executing code remain in an inactive but alert state until a task is sent to them by an adjacent processor. Processors can also be programmed to temporarily suspend a task to check for incoming tasks or messages.Type: GrantFiled: January 12, 2007Date of Patent: June 21, 2011Assignee: VNS Portfolio LLCInventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Patent number: 7934075Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously and operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The instructions executed by the computers (12) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In one application, the sleeping computer (12) is awakened by an input such that it commences an action that would otherwise required an interrupt of an otherwise active computer. For example, one computer (12f) can be used to monitor an input/output port of the computer array (10).Type: GrantFiled: May 26, 2006Date of Patent: April 26, 2011Assignee: VNS Portfolio LLCInventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Patent number: 7913069Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. Instruction words (48) can include a micro-loop (100) which is capable of performing a series of operations repeatedly. In a particular example, the series of operations are included in a single instruction word (48). The micro-loop (100) in combination with the ability of the computers (12) to send instruction words (48) to a neighboring computer (12) provides a powerful tool for allowing a computer (12) to utilize the resources of a neighboring computer (12).Type: GrantFiled: May 26, 2006Date of Patent: March 22, 2011Assignee: VNS Portfolio LLCInventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Publication number: 20100325389Abstract: A microprocessor communications system utilizes a combination of an activity status monitor register and one or more address select registers to read from a communications port of one processor and write to a communications port of an adjacent processor in a single instruction word loop. This circumvents the requirement to save and retrieve data and/or instructions from memory. A stack register selector contains a plurality of stack registers and a plurality of shift registers, which are interconnected. The stack registers are selected by the shift registers in such a way that the stack registers operate in a circular repeating pattern, which prevents overflow and underflow of stacks.Type: ApplicationFiled: April 4, 2008Publication date: December 23, 2010Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Patent number: 7617383Abstract: A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.Type: GrantFiled: August 11, 2006Date of Patent: November 10, 2009Assignee: VNS Portfolio LLCInventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Publication number: 20090265524Abstract: A method and apparatus for connecting multiple cores to form a multi core processor. Each processor is connected to at least two other processors, each of which is a mirror image of the first processor. The processors are connected to form a two dimensional matrix connected by one drop busses.Type: ApplicationFiled: April 18, 2008Publication date: October 22, 2009Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Publication number: 20080282062Abstract: A computer array (10) has a plurality of computers (12). The computers (12) communicate with each other asynchronously, and the computers (12) themselves operate in a generally asynchronous manner internally. When one computer (12) attempts to communicate with another it goes to sleep until the other computer (12) is ready to complete the transaction, thereby saving power and reducing heat production. The sleeping computer (12) can be awaiting data or instructions (12). In the case of instructions, the sleeping computer (12) can be waiting to store the instructions or to immediately execute the instructions. In the later case, the instructions are placed in an instruction register (30a) when they are received and executed therefrom, without first placing the instructions first into memory. The instructions can include a crawler (201) which is capable of traversing multiple processors along a predefined path (202) and performing a series of operations in preselected computers.Type: ApplicationFiled: May 7, 2007Publication date: November 13, 2008Inventors: Michael B. Montvelishsky, Charles H. Moore, Jeffrey Arthur Fox
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Publication number: 20070192576Abstract: A stack processor comprises a data stack with a T register, an S register, and eight hardwired bottom registers which function in a circular repeating pattern. The stack processor also comprises a return stack containing an R register, and eight hardwired bottom registers which function in a circular repeating pattern. The circular register arrays described herein eliminate overflow and underflow stack conditions.Type: ApplicationFiled: August 11, 2006Publication date: August 16, 2007Inventors: Charles H. Moore, Jeffrey Arthur Fox, John W. Rible
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Publication number: 20060127162Abstract: A disposable teeth cleaning applicator device. An elongated tubular shaft member has an applicator tip member at one end and a toothpick device at the other end. A liquid dental material is positioned inside the tubular shaft member and, once released, is squeezed or allowed to flow into the applicator tip member and used to clean a person's teeth.Type: ApplicationFiled: February 10, 2006Publication date: June 15, 2006Inventors: Rita Parikh, Arthur Fox, Diane Lorello
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Patent number: 7044671Abstract: A disposable teeth cleaning applicator device. An elongated tubular shaft member has an applicator tip member at one end and a toothpick device at the other end. A liquid dental material is positioned inside the tubular shaft member and, once released, is squeezed or allowed to flow into the applicator tip member and used to clean a person's teeth.Type: GrantFiled: September 26, 2003Date of Patent: May 16, 2006Assignee: Warner-Lambert Company LLCInventors: Rita Parikh, Arthur Fox, Diane Lorello
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Publication number: 20050069373Abstract: A disposable teeth cleaning applicator device. An elongated tubular shaft member has an applicator tip member at one end and a toothpick device at the other end. A liquid dental material is positioned inside the tubular shaft member and, once released, is squeezed or allowed to flow into the applicator tip member and used to clean a person's teeth.Type: ApplicationFiled: September 26, 2003Publication date: March 31, 2005Inventors: Rita Parikh, Arthur Fox, Diane Lorello