Patents by Inventor Arthur H. Khu
Arthur H. Khu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7685380Abstract: Individual storage locations in a PROM that stores a configuration file for a PLD may be directly addressed so that selected portions of the data stored therein may be replaced or updated with new data without having to erase all the contents of the PROM, reprogram the PROM with a new configuration file, and/or reconfigure the FPGA with the new configuration file. For some embodiments, a PROM includes a JTAG-compatible interface that is coupled to a JTAG-compatible test circuit provided within the PLD, and circuit within the PLD is configured to directly address individual storage locations in the PROM via the PROM's JTAG interface using well-known JTAG commands.Type: GrantFiled: June 29, 2005Date of Patent: March 23, 2010Assignee: XILINX, Inc.Inventor: Arthur H. Khu
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Patent number: 7555690Abstract: Various embodiments of the present invention relate to a device for testing an integrated circuit. According to one embodiment, the device comprises a first connector coupled to receive a device under test and a second connector coupled to receive compressed test data by way of test equipment. The device also comprises a decompressor coupled to receive compressed test data, and provided decompressed test data to the device under test. Embodiments implementing two different clocks to improve the speed of testing integrated circuits are also disclosed. Various methods for coupling test signals to a device under test are also disclosed.Type: GrantFiled: December 23, 2004Date of Patent: June 30, 2009Assignee: XILINX, Inc.Inventors: Yi-Ning Yang, Arthur H. Khu, Jin-Feng Chou, Paul T. Nguyen
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Patent number: 7185330Abstract: A method and system for optimizing computer source code is provided. Prior to compiling the source code, the code is analyzed to determine the occurrence of repeating patterns of code. The repeating patterns of code are replaced with a programming loop that executes a single instance of the pattern multiple times using appropriate array indices and loop increments. In this manner, source code size is reduced making transfer, storage and compiling more efficient.Type: GrantFiled: January 5, 2001Date of Patent: February 27, 2007Assignee: Xilinx, Inc.Inventor: Arthur H. Khu
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Patent number: 7117341Abstract: Prior art storage techniques have certain limitations, including requiring additional external resources to implement and not making use of all of the available storage space. A method and apparatus using a header table and, in some cases, an alternative access interface are described which allow for more efficient use of available memory space, permit an arbitrary number of data streams to be stored and accessed with a minimal interface, and provide for a simple serial connection to chain multiple memory devices together.Type: GrantFiled: May 20, 2005Date of Patent: October 3, 2006Assignee: Xilinx, Inc.Inventor: Arthur H. Khu
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Patent number: 7071848Abstract: Methods and systems are provided for dynamically compressing and decompressing a data stream in a manner that facilitates hardware implementation. In one aspect, a compression system identifies literal data sequences of variable length in the data stream and characterizes each literal sequence with an indicator that is inserted into the data stream. Sequences that repeat previous sequences in the data stream are identified and replaced with codes characterizing the repeating sequence. Another aspect provides a decompression method and system for removing indicators inserted by the compression system and replacing codes in the data stream with the repeating sequences characterized by the codes.Type: GrantFiled: May 18, 2004Date of Patent: July 4, 2006Assignee: Xilinx, Inc.Inventor: Arthur H. Khu
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Structure and method for verifying data in a non-JTAG device from a JTAG device with microcontroller
Patent number: 7047467Abstract: According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.Type: GrantFiled: April 11, 2002Date of Patent: May 16, 2006Assignee: Xilinx, Inc.Inventors: Arthur H. Khu, Farshid Shokouhi, Conrad A. Theron -
Patent number: 7047352Abstract: Structure and method for updating a system that includes a memory and a programmable logic device (PLD) retains a default PLD configuration in the memory while a new configuration is being stored in the memory, and thus protect the system from failure in case an interruption occurs while the new configuration is being stored. If a power failure interrupts the storing process, the default PLD configuration is still in the memory and can be re-loaded into the PLD and used when the system is re-started to make a further attempt at storing the new configuration. Methods are also disclosed for storing in the memory a configuration for a new PLD before the original PLD is replaced so that system hardware can be updated with minimum effort and disruption, and for dividing a directory structure into protected and unprotected regions.Type: GrantFiled: August 28, 2002Date of Patent: May 16, 2006Assignee: Xilinx, Inc.Inventors: Arthur H. Khu, Farshid Shokouhi
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Patent number: 6925583Abstract: According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.Type: GrantFiled: January 9, 2002Date of Patent: August 2, 2005Assignee: Xilinx, Inc.Inventors: Arthur H. Khu, Conrad A. Theron, Farshid Shokouhi, Pushpasheel Tawade
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Patent number: 6912646Abstract: Prior art storage techniques have certain limitations, including requiring additional external resources to implement and not making use of all of the available storage space. A method and apparatus using a header table and, in some cases, an alternative access interface are described which allow for more efficient use of available memory space, permit an arbitrary number of data streams to be stored and accessed with a minimal interface, and provide for a simple serial connection to chain multiple memory devices together.Type: GrantFiled: January 6, 2003Date of Patent: June 28, 2005Assignee: XILINX, Inc.Inventor: Arthur H. Khu
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Patent number: 6744388Abstract: Methods and systems are provided for dynamically compressing and decompressing a data stream in a manner that facilitates hardware implementation. In one aspect, a compression system identifies literal data sequences of variable length in the data stream and characterizes each literal sequence with an indicator that is inserted into the data stream. Sequences that repeat previous sequences in the data stream are identified and replaced with codes characterizing the repeating sequence. Another aspect provides a decompression method and system for removing indicators inserted by the compression system and replacing codes in the data stream with the repeating sequences characterized by the codes.Type: GrantFiled: June 19, 2002Date of Patent: June 1, 2004Assignee: Xilinx, Inc.Inventor: Arthur H. Khu
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Patent number: 5805607Abstract: A programmable logic device operable to generate different control signals during a time interval when it is being reconfigured includes a plurality of I/O pins (18a-18f), boundary scan circuitry (14) operatively connected to the I/O pins for loading a new set of data and for driving the new set of data onto the I/O pins, and means for programming (33) the programmable logic device on a row-by-row basis when loaded with program instructions. Control circuitry (31a) is provided to control the programming means to be operated on a self-timed interval for programming each row so that the boundary scan circuitry can be loaded with additional sets of data to generate the different control signals. The control circuitry includes a programming timer register (70) and a programming status register (68).Type: GrantFiled: October 22, 1996Date of Patent: September 8, 1998Assignee: Advanced Micro Devices, Inc.Inventor: Arthur H. Khu
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Patent number: 5349670Abstract: An integrated circuit programmable sequencing element apparatus on a single chip is provided which includes a PROM including first signal receiving circuitry and second signal providing circuitry; at least one feedback signal providing circuitry responsive to at least one second signal for providing at least one feedback signal; at least one input signal providing circuitry for providing at least one input signal; at least one control signal providing circuitry for providing at least one control signal; at least one programmable sequencing element circuitry for receiving said at least one control signal and the at least one input signal and for providing at least one programmable sequencing element signal; and selection circuitry for selecting at least between the at least one programmable sequencing element signal and the at least one feedback signal and for providing at least one selected signal to the first signal receiving circuitry.Type: GrantFiled: November 8, 1993Date of Patent: September 20, 1994Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Arthur H. Khu, Kapil Shankar
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Patent number: 5179716Abstract: A programmable controller which combines microaddress control logic, memory, a microinstruction decoder, and I/O into a unitary, integrated device. The microaddress control logic is responsive to sequencing signals developed by the microinstruction decoder, and includes an address generator which develops the program address. The memory, which can be either PROM or RAM, is addressed by the address and outputs a microinstruction word to a pipeline register. The microinstruction word has an internal field which is coupled to inputs of the microaddress control logic and the microinstruction decoder, and a control field which is coupled to an output buffer. The output buffer includes multiplexers which permit either the program count or the control field to be multiplexed to the output pins of the device. When the program address is multiplexed to the output pins, the programmable controller can address external memory devices.Type: GrantFiled: June 21, 1989Date of Patent: January 12, 1993Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Arthur H. Khu, William Chen
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Patent number: 4963768Abstract: A high density segmented programmable array logic device utilizes a switch interconnection matrix to couple an array of programmable logic cells. Each programmable logic cell includes programmable input logic macrocells, programmable feedback logic macrocells, programmable output logic macrocells, buried state logic macrocells and an assembly of programmable AND gates and OR gates. Each input macrocell, output macrocell and buried state macrocell has means for generating either a registered/latched output signal or a combinatorial output signal in response to an input signal to the cell. The various switches are used to couple signals to or from the assembly of programmable AND gates and OR gates.Type: GrantFiled: September 12, 1988Date of Patent: October 16, 1990Assignee: Advanced Micro Devices, Inc.Inventors: Om P. Agrawal, Kerry A. Ilgenstein, Michael J. Wright, Jerry D. Moench, Arthur H. Khu
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Patent number: 4691193Abstract: Methods are set forth for constructing encoding and decoding state machines for preselected variable length fixed rate (2,7) codes. These state machines convert a variable length code to a state dependent fixed length fixed rate (2,7) code. Methods and apparatus are also disclosed for implementing a state dependent fixed length fixed rate (2,7) coding scheme in a manner that is simpler and inherently more reliable than the implementation of the corresponding variable length fixed rate (2,7) code. In addition, the disclosed methods and apparatus for implementing the state dependent code preserve the error recovery features of a variable length fixed rate (2,7) coding scheme.Type: GrantFiled: February 7, 1986Date of Patent: September 1, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Arthur H. Khu